Clk2clock - rename the implicit "clk" module input "clock" (#387)

* Rename implict module "clk" input to "clock".
This doesn't rename all the "self-contained" test instances.
nor the memory "clk" enables,
nor the implict module "clk"s in the regress .fir files.

* Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances.
This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.

1 files changed, 3 insertions, 3 deletions

diff --git a/src/test/scala/firrtlTests/CInferMDirSpec.scala b/src/test/scala/firrtlTests/CInferMDirSpec.scala
index 1385b29d..3721543b 100644
--- a/src/test/scala/firrtlTests/CInferMDirSpec.scala
+++ b/src/test/scala/firrtlTests/CInferMDirSpec.scala
@@ -48,7 +48,7 @@ class CInferMDir extends LowTransformSpec {
     val input = """
 circuit foo :
   module foo :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
     output io : {flip wen : UInt<1>, flip in : UInt<1>, flip counter : UInt<2>, ren: UInt<1>[4], out : UInt<1>[4]}
 
@@ -56,7 +56,7 @@ circuit foo :
     cmem indices : UInt<2>[4]
     node T_0 = add(io.counter, UInt<1>("h01"))
     node temp = tail(T_0, 1)
-    infer mport index = indices[temp], clk
+    infer mport index = indices[temp], clock
     io.out[0] <= UInt<1>("h0")
     io.out[1] <= UInt<1>("h0")
     io.out[2] <= UInt<1>("h0")
@@ -65,7 +65,7 @@ circuit foo :
       io.out[index] <= io.in
     else :
       when io.wen :
-        infer mport bar = indices[temp], clk
+        infer mport bar = indices[temp], clock
         bar <= io.in
 """.stripMargin