Refactor Compilers and Transforms

* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers
* Transforms define inputForm and outputForm
* Custom transforms can be inserted at runtime into compiler or the Driver
* Current "built-in" custom transforms handled via above mechanism
* Verilog-specific passes moved to the Verilog emitter

1 files changed, 5 insertions, 6 deletions

diff --git a/src/test/scala/firrtlTests/CInferMDirSpec.scala b/src/test/scala/firrtlTests/CInferMDirSpec.scala
index 719a3334..51663eaf 100644
--- a/src/test/scala/firrtlTests/CInferMDirSpec.scala
+++ b/src/test/scala/firrtlTests/CInferMDirSpec.scala
@@ -63,13 +63,12 @@ class CInferMDir extends LowTransformSpec {
     }
   }
 
-  object CInferMDirCheck extends Transform with SimpleRun {
-    def execute(c: Circuit, map: AnnotationMap) =
-      run(c, Seq(ConstProp, CInferMDirCheckPass))
+  def transform = new PassBasedTransform {
+    def inputForm = LowForm
+    def outputForm = LowForm
+    def passSeq = Seq(ConstProp, CInferMDirCheckPass)
   }
 
-  def transform = CInferMDirCheck
-
   "Memory" should "have correct mem port directions" in {
     val input = """
 circuit foo :
@@ -97,7 +96,7 @@ circuit foo :
 
     val annotationMap = AnnotationMap(Nil)
     val writer = new java.io.StringWriter
-    compile(parse(input), annotationMap, writer)
+    compile(CircuitState(parse(input), ChirrtlForm, Some(annotationMap)), writer)
     // Check correctness of firrtl
     parse(writer.toString)
   }