diff options
| author | chick | 2020-08-14 19:47:53 -0700 |
|---|---|---|
| committer | Jack Koenig | 2020-08-14 19:47:53 -0700 |
| commit | 6fc742bfaf5ee508a34189400a1a7dbffe3f1cac (patch) | |
| tree | 2ed103ee80b0fba613c88a66af854ae9952610ce /src/test/scala/firrtlTests/CInferMDirSpec.scala | |
| parent | b516293f703c4de86397862fee1897aded2ae140 (diff) | |
All of src/ formatted with scalafmt
Diffstat (limited to 'src/test/scala/firrtlTests/CInferMDirSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/CInferMDirSpec.scala | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/src/test/scala/firrtlTests/CInferMDirSpec.scala b/src/test/scala/firrtlTests/CInferMDirSpec.scala index 6c9d4047..ce0c0a74 100644 --- a/src/test/scala/firrtlTests/CInferMDirSpec.scala +++ b/src/test/scala/firrtlTests/CInferMDirSpec.scala @@ -14,22 +14,21 @@ class CInferMDirSpec extends LowTransformSpec { def checkStmt(s: Statement): Boolean = s match { case s: DefMemory if s.name == "indices" => (s.readers contains "index") && - (s.writers contains "bar") && - s.readwriters.isEmpty + (s.writers contains "bar") && + s.readwriters.isEmpty case s: Block => - s.stmts exists checkStmt + s.stmts.exists(checkStmt) case _ => false } - def run (c: Circuit) = { + def run(c: Circuit) = { val errors = new Errors - val check = c.modules exists { - case m: Module => checkStmt(m.body) + val check = c.modules.exists { + case m: Module => checkStmt(m.body) case m: ExtModule => false } if (!check) { - errors append new PassException( - "Memory has incorrect port directions!") + errors.append(new PassException("Memory has incorrect port directions!")) errors.trigger } c |
