diff options
| author | Schuyler Eldridge | 2020-04-22 20:26:11 -0400 |
|---|---|---|
| committer | GitHub | 2020-04-22 20:26:11 -0400 |
| commit | 404d419a42c33ce4a68eedce636c336adf7d53be (patch) | |
| tree | 607b55e30774227895c75b60fb8fd67845ed23a8 /src/test/scala/firrtl/testutils/FirrtlSpec.scala | |
| parent | 65360f886f9b92438d1b6fe609120b34ebb413cf (diff) | |
| parent | ffa6958535292d636923739d9d77b566054e2208 (diff) | |
Merge pull request #1537 from freechipsproject/optionalPrerequisitesOf
Change `dependents` to `optionalPrerequisiteOf`
Diffstat (limited to 'src/test/scala/firrtl/testutils/FirrtlSpec.scala')
| -rw-r--r-- | src/test/scala/firrtl/testutils/FirrtlSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/firrtl/testutils/FirrtlSpec.scala b/src/test/scala/firrtl/testutils/FirrtlSpec.scala index 1dc56b15..e14dc78c 100644 --- a/src/test/scala/firrtl/testutils/FirrtlSpec.scala +++ b/src/test/scala/firrtl/testutils/FirrtlSpec.scala @@ -39,7 +39,7 @@ object RenameTop extends Transform with PreservesAll[Transform] { override val optionalPrerequisites = Seq(Dependency[RenameModules]) - override val dependents = Seq(Dependency[VerilogEmitter], Dependency[MinimumVerilogEmitter]) + override val optionalPrerequisiteOf = Seq(Dependency[VerilogEmitter], Dependency[MinimumVerilogEmitter]) def execute(state: CircuitState): CircuitState = { val c = state.circuit |