Merge branch 'master' into update/sbt-scalafix-0.9.28

5 files changed, 179 insertions, 13 deletions

diff --git a/src/main/scala/firrtl/annotations/Annotation.scala b/src/main/scala/firrtl/annotations/Annotation.scala
index b5c9c7e0..08555a84 100644
--- a/src/main/scala/firrtl/annotations/Annotation.scala
+++ b/src/main/scala/firrtl/annotations/Annotation.scala
@@ -5,6 +5,8 @@ package annotations
 
 import firrtl.options.StageUtils
 
+import scala.collection.Traversable
+
 case class AnnotationException(message: String) extends Exception(message)
 
 /** Base type of auxiliary information */
@@ -23,18 +25,19 @@ trait Annotation extends Product {
     * @param ls
     * @return
     */
-  private def extractComponents(ls: scala.collection.Traversable[_]): Seq[Target] = {
-    ls.collect {
+  private def extractComponents(ls: Traversable[_]): Traversable[Target] = {
+    ls.flatMap {
       case c: Target                          => Seq(c)
-      case o: Product                         => extractComponents(o.productIterator.toIterable)
       case x: scala.collection.Traversable[_] => extractComponents(x)
-    }.foldRight(Seq.empty[Target])((seq, c) => c ++ seq)
+      case o: Product                         => extractComponents(o.productIterator.toIterable)
+      case _ => Seq()
+    }
   }
 
   /** Returns all [[firrtl.annotations.Target Target]] members in this annotation
     * @return
     */
-  def getTargets: Seq[Target] = extractComponents(productIterator.toSeq)
+  def getTargets: Seq[Target] = extractComponents(productIterator.toIterable).toSeq
 }
 
 /** If an Annotation does not target any [[Named]] thing in the circuit, then all updates just
@@ -42,12 +45,17 @@ trait Annotation extends Product {
   */
 trait NoTargetAnnotation extends Annotation {
   def update(renames: RenameMap): Seq[NoTargetAnnotation] = Seq(this)
+
+  override def getTargets: Seq[Target] = Seq.empty
 }
 
 /** An Annotation that targets a single [[Named]] thing */
 trait SingleTargetAnnotation[T <: Named] extends Annotation {
   val target: T
 
+  // we can implement getTargets more efficiently since we know that we have exactly one target
+  override def getTargets: Seq[Target] = Seq(target)
+
   /** Create another instance of this Annotation */
   def duplicate(n: T): Annotation
 
@@ -100,6 +108,8 @@ trait MultiTargetAnnotation extends Annotation {
     */
   def targets: Seq[Seq[Target]]
 
+  override def getTargets: Seq[Target] = targets.flatten
+
   /** Create another instance of this Annotation
     *
     * The inner Seqs correspond to the renames of the inner Seqs of targets
diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala
index 912acf8e..78b3ce36 100644
--- a/src/main/scala/firrtl/passes/Inline.scala
+++ b/src/main/scala/firrtl/passes/Inline.scala
@@ -179,7 +179,7 @@ class InlineInstances extends Transform with DependencyAPIMigration with Registe
 
     /** Add a prefix to all declarations updating a [[Namespace]] and appending to a [[RenameMap]] */
     def appendNamePrefix(
-      currentModule: IsModule,
+      currentModule: InstanceTarget,
       nextModule:    IsModule,
       prefix:        String,
       ns:            Namespace,
@@ -197,8 +197,13 @@ class InlineInstances extends Transform with DependencyAPIMigration with Registe
           }
           ofModuleOpt match {
             case None =>
+              renameMap.record(currentModule.ofModuleTarget.ref(name), nextModule.ref(prefix + name))
               renameMap.record(currentModule.ref(name), nextModule.ref(prefix + name))
             case Some(ofModule) =>
+              renameMap.record(
+                currentModule.ofModuleTarget.instOf(name, ofModule),
+                nextModule.instOf(prefix + name, ofModule)
+              )
               renameMap.record(currentModule.instOf(name, ofModule), nextModule.instOf(prefix + name, ofModule))
           }
           renames(name) = prefix + name
@@ -348,7 +353,6 @@ class InlineInstances extends Transform with DependencyAPIMigration with Registe
             .map(appendRefPrefix(inlineTarget, prefixMap))
 
           renames.record(inlineTarget, currentModule)
-
           renamedBody
         case sx =>
           sx
diff --git a/src/main/scala/firrtl/passes/memlib/DumpMemoryAnnotations.scala b/src/main/scala/firrtl/passes/memlib/DumpMemoryAnnotations.scala
index 5cc1e0bf..f88e7e39 100644
--- a/src/main/scala/firrtl/passes/memlib/DumpMemoryAnnotations.scala
+++ b/src/main/scala/firrtl/passes/memlib/DumpMemoryAnnotations.scala
@@ -4,7 +4,9 @@ package firrtl
 package passes
 package memlib
 
+import firrtl.annotations.{CircuitName, ModuleName}
 import firrtl.stage.Forms
+import firrtl.transforms.BlackBoxInlineAnno
 
 class DumpMemoryAnnotations extends Transform with DependencyAPIMigration {
 
@@ -13,16 +15,146 @@ class DumpMemoryAnnotations extends Transform with DependencyAPIMigration {
   override def optionalPrerequisiteOf = Forms.MidEmitters
   override def invalidates(a: Transform) = false
 
+  private def vlsiMemGen(annotatedMemory: DefAnnotatedMemory, genBlackBox: Boolean): (String, String) = {
+    // MaskedWritePort => WritePort with masked = true
+    case class Port(prefix: String, portType: MemPort)
+
+    val masked = annotatedMemory.maskGran.isDefined
+
+    val name = annotatedMemory.name
+    val width = {
+      val width = bitWidth(annotatedMemory.dataType)
+      require(width <= Int.MaxValue)
+      width.toInt
+    }
+    val depth = annotatedMemory.depth.toInt
+    val maskGran = if (masked) {
+      val maskGran = annotatedMemory.maskGran.get
+      require(maskGran <= Int.MaxValue)
+      maskGran.toInt
+    } else width
+    val maskSeg = width / maskGran
+    val ports = annotatedMemory.readers.indices.map(number => Port(s"R${number}_", ReadPort)) ++
+      annotatedMemory.writers.indices.map(number => Port(s"W${number}_", WritePort)) ++
+      annotatedMemory.readwriters.indices.map(number => Port(s"RW${number}_", ReadWritePort))
+
+    val addrWidth = math.max(math.ceil(math.log(depth) / math.log(2)).toInt, 1)
+    val readPorts = ports.filter(port => port.portType == ReadPort || port.portType == ReadWritePort)
+
+    val portSpec = ports.flatMap(port =>
+      Seq(s"input ${port.prefix}clk", s"input [${addrWidth - 1}:0] ${port.prefix}addr", s"input ${port.prefix}en") ++
+        ((port, masked) match {
+          case (Port(prefix, ReadPort), _)      => Seq(s"output [${width - 1}:0] ${prefix}data")
+          case (Port(prefix, WritePort), false) => Seq(s"input [${width - 1}:0] ${prefix}data")
+          case (Port(prefix, WritePort), true) =>
+            Seq(s"input [${width - 1}:0] ${prefix}data", s"input [${maskSeg - 1}:0] ${prefix}mask")
+          case (Port(prefix, ReadWritePort), false) =>
+            Seq(
+              s"input ${prefix}wmode",
+              s"input [${width - 1}:0] ${prefix}wdata",
+              s"output [${width - 1}:0] ${prefix}rdata"
+            )
+          case (Port(prefix, ReadWritePort), true) =>
+            Seq(
+              s"input ${prefix}wmode",
+              s"input [${maskSeg - 1}:0] ${prefix}wmask",
+              s"input [${width - 1}:0] ${prefix}wdata",
+              s"output [${width - 1}:0] ${prefix}rdata"
+            )
+        })
+    )
+
+    val decl = readPorts.flatMap(port =>
+      Seq(s"reg reg_${port.prefix}ren;", s"reg [${addrWidth - 1}:0] reg_${port.prefix}addr;")
+    ) ++ Seq(
+      s"reg [${width - 1}:0] ram [${depth - 1}:0];",
+      "`ifdef RANDOMIZE_MEM_INIT",
+      "  integer initvar;",
+      "  initial begin",
+      "    #`RANDOMIZE_DELAY begin end",
+      s"    for (initvar = 0; initvar < $depth; initvar = initvar+1)",
+      s"      ram[initvar] = {${(width - 1) / 32 + 1} {$$random}};"
+    ) ++ readPorts.map(port => s"    reg_${port.prefix}addr = {${(addrWidth - 1) / 32 + 1} {$$random}};") ++ Seq(
+      "  end",
+      "`endif"
+    )
+
+    val sequential = {
+      def genReadSequential(en: String, prefix: String): Seq[String] = Seq(
+        s"always @(posedge ${prefix}clk)",
+        s"  reg_${prefix}ren <= $en;",
+        s"always @(posedge ${prefix}clk)",
+        s"  if ($en) reg_${prefix}addr <= ${prefix}addr;"
+      )
+      def genWriteSequential(en: String, prefix: String, inputData: String, maskName: String): Seq[String] = Seq(
+        s"always @(posedge ${prefix}clk)",
+        s"  if ($en) begin"
+      ) ++ (0 until maskSeg).map { i =>
+        val ifMask = if (masked) s"if (${prefix}${maskName}[$i]) " else ""
+        val ram_range = s"${(i + 1) * maskGran - 1}:${i * maskGran}"
+        s"    ${ifMask}ram[${prefix}addr][$ram_range] <= ${prefix}$inputData[$ram_range];"
+      } ++ Seq("  end")
+      ports.flatMap(port =>
+        port.portType match {
+          case ReadPort  => genReadSequential(port.prefix + "en", port.prefix)
+          case WritePort => genWriteSequential(port.prefix + "en", port.prefix, "data", "mask")
+          case ReadWritePort =>
+            genReadSequential(s"${port.prefix}en && !${port.prefix}wmode", port.prefix) ++
+              genWriteSequential(s"${port.prefix}en && ${port.prefix}wmode", port.prefix, "wdata", "wmask")
+        }
+      )
+    }
+
+    val combinational = readPorts.flatMap { port =>
+      val data = port.prefix + (if (port.portType == ReadWritePort) "rdata" else "data")
+      Seq(
+        "`ifdef RANDOMIZE_GARBAGE_ASSIGN",
+        s"reg [${((width - 1) / 32 + 1) * 32 - 1}:0] ${port.prefix}random;",
+        "`ifdef RANDOMIZE_MEM_INIT",
+        "  initial begin",
+        "    #`RANDOMIZE_DELAY begin end",
+        s"    ${port.prefix}random = {${Seq.fill((width - 1) / 32 + 1)("$random").mkString(", ")}};",
+        s"    reg_${port.prefix}ren = ${port.prefix}random[0];",
+        "  end",
+        "`endif",
+        s"always @(posedge ${port.prefix}clk) ${port.prefix}random <= {${Seq.fill((width - 1) / 32 + 1)("$random").mkString(", ")}};",
+        s"assign $data = reg_${port.prefix}ren ? ram[reg_${port.prefix}addr] : ${port.prefix}random[${width - 1}:0];",
+        "`else",
+        s"assign $data = ram[reg_${port.prefix}addr];",
+        "`endif"
+      )
+    }
+
+    val body = if (genBlackBox) "" else s"""
+                                           |  ${decl.mkString("\n  ")}
+                                           |  ${sequential.mkString("\n  ")}
+                                           |  ${combinational.mkString("\n  ")}""".stripMargin
+
+    (name, s"""// name:$name depth:$depth width:$width masked:$masked maskGran:$maskGran maskSeg:$maskSeg
+              |module $name(
+              |  ${portSpec.mkString(",\n  ")}
+              |);
+              |
+              |$body
+              |
+              |endmodule""".stripMargin)
+  }
+
   def execute(state: CircuitState): CircuitState = {
     state.copy(annotations = state.annotations.flatMap {
       // convert and remove AnnotatedMemoriesAnnotation to CustomFileEmission
       case AnnotatedMemoriesAnnotation(annotatedMemories) =>
         state.annotations.collect {
           case a: MemLibOutConfigFileAnnotation =>
-            a.copy(annotatedMemories = annotatedMemories)
-          // todo convert xxx to verilogs here.
-        }
+            Seq(a.copy(annotatedMemories = annotatedMemories))
+          case GenVerilogMemBehaviorModelAnno(genBlackBox) =>
+            annotatedMemories.map(vlsiMemGen(_, genBlackBox)).map {
+              case (name, content) =>
+                BlackBoxInlineAnno(ModuleName(name, CircuitName(state.circuit.main)), name + ".v", content)
+            }
+        }.flatten
       case MemLibOutConfigFileAnnotation(_, Nil) => Nil
+      case GenVerilogMemBehaviorModelAnno(_)     => Nil
       case a                                     => Seq(a)
     })
   }
diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala
index f9df27a7..c7b0fbcd 100644
--- a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala
+++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala
@@ -6,9 +6,10 @@ package memlib
 import firrtl.Utils.error
 import firrtl._
 import firrtl.annotations._
-import firrtl.options.{CustomFileEmission, HasShellOptions, ShellOption}
+import firrtl.options.{CustomFileEmission, Dependency, HasShellOptions, ShellOption}
 import firrtl.passes.wiring._
 import firrtl.stage.{Forms, RunFirrtlTransformAnnotation}
+import firrtl.transforms.BlackBoxSourceHelper
 
 import java.io.{CharArrayWriter, PrintWriter}
 
@@ -46,6 +47,8 @@ object PassConfigUtil {
 
 case class ReplSeqMemAnnotation(inputFileName: String, outputConfig: String) extends NoTargetAnnotation
 
+case class GenVerilogMemBehaviorModelAnno(genBlackBox: Boolean) extends NoTargetAnnotation
+
 /** Generate conf file for a sequence of [[DefAnnotatedMemory]]
   * @note file already has its suffix adding by `--replSeqMem`
   */
@@ -131,6 +134,20 @@ class ReplSeqMem extends SeqTransform with HasShellOptions with DependencyAPIMig
       helpText = "Blackbox and emit a configuration file for each sequential memory",
       shortOption = Some("frsq"),
       helpValueName = Some("-c:<circuit>:-i:<file>:-o:<file>")
+    ),
+    new ShellOption[String](
+      longOption = "gen-mem-verilog",
+      toAnnotationSeq = (a: String) =>
+        Seq(
+          a match {
+            case "blackbox" => GenVerilogMemBehaviorModelAnno(genBlackBox = true)
+            case _          => GenVerilogMemBehaviorModelAnno(genBlackBox = false)
+          },
+          RunFirrtlTransformAnnotation(new ReplSeqMem)
+        ),
+      helpText = "Blackbox and emit a Verilog behavior model for each sequential memory",
+      shortOption = Some("gmv"),
+      helpValueName = Some("<blackbox|full>")
     )
   )
 
@@ -144,6 +161,7 @@ class ReplSeqMem extends SeqTransform with HasShellOptions with DependencyAPIMig
       new ResolveMemoryReference,
       new ReplaceMemMacros,
       new WiringTransform,
-      new DumpMemoryAnnotations
+      new DumpMemoryAnnotations,
+      new BlackBoxSourceHelper
     )
 }
diff --git a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala
index 86afe520..d8b8eed9 100644
--- a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala
+++ b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala
@@ -40,7 +40,9 @@ class WiringTransform extends Transform with DependencyAPIMigration {
 
   override def prerequisites = Forms.MidForm
   override def optionalPrerequisites = Seq.empty
-  override def optionalPrerequisiteOf = Forms.MidEmitters
+  override def optionalPrerequisiteOf = Forms.MidEmitters ++
+    // once wire targets are turned into nodes, our logic to wire them up no longer works
+    Seq(Dependency[firrtl.transforms.RemoveWires])
 
   private val invalidates = Forms.VerilogOptimized.toSet -- Forms.MinimalHighForm
   override def invalidates(a: Transform): Boolean = invalidates(Dependency.fromTransform(a))