diff options
| author | Adam Izraelevitz | 2015-10-06 14:36:51 -0700 |
|---|---|---|
| committer | Adam Izraelevitz | 2015-10-06 14:36:51 -0700 |
| commit | eb79a51cadcee109c4bcf727762027ba85aba36a (patch) | |
| tree | a2d52d8697b87b1d07615dc9153d3a4da1b6c95f /src/main/stanza/verilog.stanza | |
| parent | 2485d20374166b27c06c475a4aef365761a818f7 (diff) | |
| parent | aa8cfe06fd76d47e3b3721aae6ccf6b39dda34b8 (diff) | |
Merge pull request #45 from ucb-bar/change-mem-type
Changed DefMemory to be a non-vector type with a size member
Diffstat (limited to 'src/main/stanza/verilog.stanza')
| -rw-r--r-- | src/main/stanza/verilog.stanza | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza index 1a495835..ef78659a 100644 --- a/src/main/stanza/verilog.stanza +++ b/src/main/stanza/verilog.stanza @@ -221,10 +221,9 @@ defn emit-module (m:InModule) : val w = width!(type(s)) add(inits,[sym " = " rand-string(w)]) (s:DefMemory) : - val vtype = type(s) as VectorType - add(regs,["reg " get-width(type(vtype)) " " sym " [0:" size(vtype) - 1 "];"]) - add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"]) - add(inits,[" " sym "[initvar] = " rand-string(width!(type(vtype))) ]) + add(regs,["reg " get-width(type(s)) " " sym " [0:" size(s) - 1 "];"]) + add(inits,["for (initvar = 0; initvar < " size(s) "; initvar = initvar+1)"]) + add(inits,[" " sym "[initvar] = " rand-string(width!(type(s))) ]) (s:DefNode) : add(wires,["wire " get-width(type(value(s))) " " sym ";"]) add(assigns,["assign " sym " = " emit(value(s)) ";"]) @@ -252,11 +251,11 @@ defn emit-module (m:InModule) : updates[get-name(clock(mem-declaration))] = my-clk-update ; emit read accessor - add(wires,["wire " get-width(type(type(source(s)) as VectorType)) " " sym ";"]) + add(wires,["wire " get-width(type(source(s))) " " sym ";"]) add(assigns,["assign " sym " = " emit(source(s)) "[" emit(index*) "];"]) else : ; emit read accessor - add(wires,["wire " get-width(type(type(source(s)) as VectorType)) " " sym ";"]) + add(wires,["wire " get-width(type(source(s))) " " sym ";"]) add(assigns,["assign " sym " = " emit(source(s)) "[" emit(index(s)) "];"]) WRITE : val my-clk-update = get?(updates,get-name(clock(mem-declaration)),Vector<Streamable>()) |