merge + fix trim to use correct bits operands

1 files changed, 67 insertions, 23 deletions

diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza
index 19472573..bee10177 100644
--- a/src/main/stanza/verilog.stanza
+++ b/src/main/stanza/verilog.stanza
@@ -38,6 +38,11 @@ defn remove-subfield (e:Expression) -> Expression :
       (e:Subfield) : Ref(to-symbol $ string-join $ [emit(exp(e)) "_" name(e)],type(e))
       (e) : e
 
+definterface VKind
+defstruct WireKind <: VKind 
+defstruct RegKind <: VKind
+defstruct SeqMemKind <: VKind
+defstruct ComMemKind <: VKind
 
 ;============ Verilog Backend =============
 
@@ -109,7 +114,24 @@ defn emit (e:Expression) -> String :
                v = concat(v, [" ^ " emit(x)])
             v
 
-defn emit-module (m:Module) :
+defn emit-module (m:InModule) :
+   val h = HashTable<Symbol,VKind>(symbol-hash)
+   defn build-table (m:InModule) :
+      defn build-table (s:Stmt) -> Stmt :
+         match(map(build-table,s)) : 
+            (s:DefWire) : h[name(s)] = WireKind()
+            (s:DefMemory) : 
+               if seq?(s) : h[name(s)] = SeqMemKind()
+               else       : h[name(s)] = ComMemKind()
+            (s:Connect) : 
+               match(exp(s)) :
+                  (e:Register) : h[name(loc(s) as Ref)] = RegKind()
+                  (e) : false
+            (s) : false
+         s
+      build-table(body(m))
+   build-table(m)
+
    val wires = Vector<Streamable>()
    val regs = Vector<Streamable>()
    val inits = Vector<Streamable>()
@@ -117,39 +139,36 @@ defn emit-module (m:Module) :
    val updates = Vector<Streamable>()
    val insts = HashTable<Symbol,Symbol>(symbol-hash) ; inst -> module
    val inst-ports = HashTable<Symbol,Vector<Streamable>>(symbol-hash)
+
+   val sh = get-sym-hash(m)
    
    defn emit-s (s:Stmt) :
       match(map(remove-subfield,s)) :
-         (s:DefWire) : add(wires,["wire " get-width(type(s)) " " name(s) ";"])
+         (s:DefWire) : 
+            if h[name(s)] == RegKind() : 
+               add(regs,["reg  " get-width(type(s)) " " name(s) ";"])
+            else :
+               add(wires,["wire " get-width(type(s)) " " name(s) ";"])
          (s:DefInstance) : 
             inst-ports[name(s)] = Vector<Streamable>()
             insts[name(s)] = name(module(s) as Ref)
             for f in fields(type(module(s)) as BundleType) do :
-               ;val sf = value(s) as Subfield
-               ;val e = exp(sf) as Ref
                val n* = to-symbol $ string-join $ [name(s) "_" name(f)]
                add(wires,["wire " get-width(type(f)) " " n* ";"])
                add(inst-ports[name(s)], ["." name(f) "( " n* " )"])
          (s:DefMemory) :
             val vtype = type(s) as VectorType
-            val innerwidth = 
-            add(regs,["reg  " get-width(type(vtype)) " " name(s) " [0:" size(vtype) "];"])
-            add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"])
-            add(inits,[name(s) " = {" width!(type(vtype)) "{$random}};"])
-         (s:DefNode) :
-            if value(s) typeof Register :
-               val reg = value(s) as Register
-               add(regs,["reg  " get-width(type(reg)) " " name(s) ";"])
-               add(inits,[name(s) " = {" width!(type(reg)) "{$random}};"])
-               add(updates,["if(" emit(enable(reg)) ") begin"])
-               add(updates,["  " name(s) " <= " emit(value(reg)) ";"])
-               add(updates,["end"])
-            else if value(s) typeof ReadPort :
-               val rp = value(s) as ReadPort
-               add(assigns,["assign " name(s) " = " emit(mem(rp)) "[" emit(index(rp)) "];"])
+            if seq?(s) :
+               add(regs,["reg  " get-width(type(vtype)) " " name(s) " [0:" size(vtype) "];"])
+               add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"])
+               add(inits,[name(s) " = {" width!(type(vtype)) "{$random}};"])
             else :
-               add(wires,["wire " get-width(type(value(s))) " " name(s) ";"])
-               add(assigns,["assign " name(s) " = " emit(value(s)) ";"])
+               add(regs,["reg  " get-width(type(vtype)) " " name(s) " [0:" size(vtype) "];"])
+               add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"])
+               add(inits,[name(s) " = {" width!(type(vtype)) "{$random}};"])
+         (s:DefNode) :
+            add(wires,["wire " get-width(type(value(s))) " " name(s) ";"])
+            add(assigns,["assign " name(s) " = " emit(value(s)) ";"])
          (s:Begin) : do(emit-s, body(s))
          (s:Connect) : 
             if loc(s) typeof WritePort :
@@ -158,7 +177,29 @@ defn emit-module (m:Module) :
                add(updates,["  " emit(mem(wp)) "[" emit(index(wp)) "] <= " emit(exp(s)) ";"])
                add(updates,["end"])
             else :
-               add(assigns,["assign " emit(loc(s)) " = " emit(exp(s)) ";"])
+               if exp(s) typeof Register :
+                  val n = name(loc(s) as Ref)
+                  val reg = exp(s) as Register
+                  add(inits,[n " = {" width!(type(reg)) "{$random}};"])
+                  add(updates,["if(" emit(enable(reg)) ") begin"])
+                  add(updates,["  " n " <= " emit(value(reg)) ";"])
+                  add(updates,["end"])
+               else if exp(s) typeof ReadPort :
+                  val n = name(loc(s) as Ref)
+                  val rp = exp(s) as ReadPort
+                  match(h[name(mem(rp) as Ref)]) :
+                     (k:SeqMemKind) : 
+                        val index* = Ref(firrtl-gensym(name(index(rp) as Ref),sh),type(index(rp)))
+                        add(regs,[ "reg  " get-width(type(index*)) " " name(index*) ";"])
+                        add(inits,[name(index*) " = {" width!(type(index*)) "{$random}};"])
+                        add(updates,["if(" emit(enable(rp)) ") begin"])
+                        add(updates,["  " name(index*) " <= " emit(index(rp)) ";"])
+                        add(updates,["end"])
+                        add(assigns,["assign " n " = " emit(mem(rp)) "[" emit(index*) "];"])
+                     (k:ComMemKind) : 
+                        add(assigns,["assign " n " = " emit(mem(rp)) "[" emit(index(rp)) "];"])
+               else :
+                  add(assigns,["assign " emit(loc(s)) " = " emit(exp(s)) ";"])
          (s) : s 
    
    emit-s(body(m))
@@ -219,5 +260,8 @@ defn emit-module (m:Module) :
 public defn emit-verilog (file:String, c:Circuit) :
    with-output-file{file, _} $ fn () :
       for m in modules(c) do :
-         emit-module(m)
+         match(m) :
+            (m:InModule) : emit-module(m)
+            (m:ExModule) : false
+
    c