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authorazidar2015-08-25 14:51:08 -0700
committerazidar2015-08-25 14:51:08 -0700
commit9fd6d47c5ee82e4dac924e15b60f2a519d566b14 (patch)
tree999ea3f223d228cef7f84ae7647ec95db7294e56 /src/main/stanza/verilog.stanza
parenteb1ab67b6cc3fd4a549da563bf643bd519d7562e (diff)
Removed IntWidth, now only use LongWidth. Now do width inference for Constants in parser, and correctly subtract 1 (except when 0) when calculating width from num-bits of BigInt
Diffstat (limited to 'src/main/stanza/verilog.stanza')
-rw-r--r--src/main/stanza/verilog.stanza6
1 files changed, 1 insertions, 5 deletions
diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza
index 053b78e7..1223026e 100644
--- a/src/main/stanza/verilog.stanza
+++ b/src/main/stanza/verilog.stanza
@@ -16,7 +16,6 @@ public defmethod short-name (b:Verilog) -> String : "To Verilog"
defn width! (w:Width) -> Long :
match(w) :
- (w:IntWidth) : to-long(width(w))
(w:LongWidth) : width(w)
(w) : error("Non-supported width type.")
@@ -28,9 +27,6 @@ defn width! (t:Type) -> Long :
defn emit (w:Width) -> String :
match(w) :
- (w:IntWidth) :
- if width(w) >= 1 : string-join $ ["[" width(w) - 1 ":0]"] ;TODO check if need to special case 0 or 1 width wires
- else : ""
(w:LongWidth) :
if width(w) >= to-long(1) : string-join $ ["[" width(w) - to-long(1) ":0]"] ;TODO check if need to special case 0 or 1 width wires
else : ""
@@ -41,7 +37,7 @@ defn get-width (t:Type) -> String :
match(t) :
(t:UIntType) : emit(width(t))
(t:SIntType) : emit(width(t))
- (t:ClockType) : emit(IntWidth(1))
+ (t:ClockType) : emit(LongWidth(1))
(t) : error("Non-supported type.")
defn remove-subfield (e:Expression) -> Expression :