diff options
| author | azidar | 2015-07-13 16:22:43 -0700 |
|---|---|---|
| committer | azidar | 2015-07-13 16:22:43 -0700 |
| commit | 9b6d8514a3be860562d8d524fa425c87d1537e8a (patch) | |
| tree | ca46b9703046e23068860b5c5d8d6af01296c000 /src/main/stanza/verilog.stanza | |
| parent | 1ed6d4a47c92072b12db4b784f239071e4928049 (diff) | |
Added tests for clocks. Added remove scope and special chars passes. Added tests. Made more tests pass
Diffstat (limited to 'src/main/stanza/verilog.stanza')
| -rw-r--r-- | src/main/stanza/verilog.stanza | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza index 23591f45..29112271 100644 --- a/src/main/stanza/verilog.stanza +++ b/src/main/stanza/verilog.stanza @@ -249,6 +249,7 @@ defn emit-module (m:InModule) : OUTPUT : print-all([port-indent "output " get-width(type(p)) " " name(p) end]) add(assigns,["assign " name(p) " = " emit(cons[name(p)]) ";"]) + if length(ports(m)) == 0 : print(");\n") for w in wires do : print(" ") |