Added verilog keywords to uniquify them

1 files changed, 7 insertions, 6 deletions

diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza
index cbfd6d8b..aa755ed5 100644
--- a/src/main/stanza/verilog.stanza
+++ b/src/main/stanza/verilog.stanza
@@ -13,6 +13,7 @@ public defmethod name (b:Verilog) -> String : "To Verilog"
 public defmethod short-name (b:Verilog) -> String : "To Verilog"
 
 ;============ Utilz =============
+
 defn width! (w:Width) -> Long :
    match(w) : 
       (w:IntWidth) : to-long(width(w))
@@ -48,6 +49,12 @@ defn remove-subfield (e:Expression) -> Expression :
       (e:Subfield) : Ref(to-symbol $ string-join $ [emit(exp(e)) bundle-expand-delin name(e)],type(e))
       (e) : e
 
+defn get-name (e:Expression) -> Symbol :
+   match(e) :
+      (e:Ref) : name(e)
+      (e:Subfield) : error("Shouldn't be here")
+      (e) : error("Shouldn't be here")
+
 ;============ Verilog Backend =============
 
 defn emit-as-type (e:Expression,t:Type) -> String : 
@@ -150,12 +157,6 @@ defn emit (e:Expression) -> String :
                   v = concat(v, [" ^ " emit(x)])
                v
 
-defn get-name (e:Expression) -> Symbol :
-   match(e) :
-      (e:Ref) : name(e)
-      (e:Subfield) : error("Shouldn't be here")
-      (e) : error("Shouldn't be here")
-
 defn emit-module (m:InModule) :
    val vdecs = Vector<KeyValue<Symbol,Stmt>>() ; all declarations in order, to preserve ordering
    val decs = HashTable<Symbol,Stmt>(symbol-hash) ; all declarations, for fast lookups