Added Printf and Stop to firrtl. #23 #24.

1 files changed, 43 insertions, 3 deletions

diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza
index ef78659a..5cf42323 100644
--- a/src/main/stanza/verilog.stanza
+++ b/src/main/stanza/verilog.stanza
@@ -54,6 +54,20 @@ defn get-name (e:Expression) -> Symbol :
       (e:Subfield) : error("Shouldn't be here")
       (e) : error("Shouldn't be here")
 
+defn escape (s:String) -> String :
+  val s* = Vector<String>()
+  add(s*,"\"");"
+  var percent = false
+  for c in s do :
+     if c == '\n' :
+        add(s*,"\\n")
+     else :
+        if c == 'x' and percent :
+           add(s*,"h")
+        else : add(s*,to-string(c))
+     percent = c == '%'
+  add(s*,"\"");"
+  string-join(s*)
 ;============ Verilog Backend =============
 
 defn emit-as-type (e:Expression,t:Type) -> String : 
@@ -168,15 +182,32 @@ defn emit-module (m:InModule) :
    val decs = HashTable<Symbol,Stmt>(symbol-hash) ; all declarations, for fast lookups
    val cons = HashTable<Symbol,Expression>(symbol-hash) ; all connections
    val ens = HashTable<Symbol,Expression>(symbol-hash) ; all enables
+   val simuls = Vector<Streamable>()
    defn build-table (s:Stmt) -> False :
       match(s) :
          (s:DefWire|DefPoison|DefRegister|DefAccessor|DefMemory|DefNode|DefInstance) : 
             add(vdecs,name(s) => s)
             decs[name(s)] = s
          (s:Conditionally) : 
-            val n = get-name(loc(conseq(s) as Connect))
-            ens[n] = pred(s)
-            cons[n] = exp(conseq(s) as Connect)
+            match(conseq(s)) :
+               (c:Connect) :
+                  val n = get-name(loc(c))
+                  ens[n] = pred(s)
+                  cons[n] = exp(conseq(s) as Connect)
+               (c:PrintfStmt) :
+                  add(simuls,["if(" emit(pred(s)) ") begin"])
+                  add(simuls,["  $fdisplay(32/'h80000002," string-join(List(escape(string(c)),map(emit,args(c))), ", ") ");"])
+                  add(simuls,["end"])
+               (c:StopStmt) : 
+                  add(simuls,["if(" emit(pred(s)) ") begin"])
+                  add(simuls,["  $fdisplay(32/'h80000002," ret(c) ");"])
+                  add(simuls,["  $finish;"])
+                  add(simuls,["end"])
+         (s:PrintfStmt) : 
+            add(simuls,["$fdisplay(32/'h80000002," string-join(List(escape(string(s)),map(emit,args(s))), ", ") ");"])
+         (c:StopStmt) : 
+            add(simuls,["$fdisplay(32/'h80000002," ret(c) ");"])
+            add(simuls,["$finish;"])
          (s:Connect) : 
             val n = get-name(loc(s))
             cons[n] = exp(s)
@@ -321,6 +352,15 @@ defn emit-module (m:InModule) :
             print("    ")
             println-all(u)
          println("  end")
+
+   if length(simuls) != 0 :
+      println("`ifndef SYNTHESIS")
+      println("  always @(*) begin")
+      for x in simuls do :
+         print("    ")
+         println-all(x)
+      println("  end")
+      println("`endif")
       
    println("endmodule")