diff options
| author | Adam Izraelevitz | 2015-07-21 17:30:43 -0700 |
|---|---|---|
| committer | Adam Izraelevitz | 2015-07-21 17:30:43 -0700 |
| commit | 5fadf1210fb358e1f9aff628da8d369efdde9b4e (patch) | |
| tree | b7819b114ec0b42021a47cef77fc9dd2271d67d4 /src/main/stanza/verilog.stanza | |
| parent | 86dfd891ee40a9ff367984ec285013cc8e5b37c3 (diff) | |
Firrtl generates verilog that compiles, but does not work
Diffstat (limited to 'src/main/stanza/verilog.stanza')
| -rw-r--r-- | src/main/stanza/verilog.stanza | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza index 2921c964..50794eeb 100644 --- a/src/main/stanza/verilog.stanza +++ b/src/main/stanza/verilog.stanza @@ -197,17 +197,14 @@ defn emit-module (m:InModule) : add(my-clk-update,[sym " <= " emit(cons[sym]) ";"]) updates[get-name(clock(s))] = my-clk-update (s:DefMemory) : - println(STANDARD-ERROR, s) val vtype = type(s) as VectorType add(regs,["reg " get-width(type(vtype)) " " sym " [0:" size(vtype) "];"]) add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"]) add(inits,[" " sym "[initvar] = {" width!(type(vtype)) "{$random}};"]) (s:DefNode) : - println(STANDARD-ERROR, s) add(wires,["wire " get-width(type(value(s))) " " sym ";"]) add(assigns,["assign " sym " = " emit(value(s)) ";"]) (s:DefInstance) : - println(STANDARD-ERROR, s) inst-ports[sym] = Vector<Streamable>() insts[sym] = name(module(s) as Ref) for f in fields(type(module(s)) as BundleType) do : |