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| author | azidar | 2016-01-16 15:47:37 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 15:47:37 -0800 |
| commit | df1bb3aced1e560dd919460a846c28ad2deacbd3 (patch) | |
| tree | 29a8d7d726acf9ad810c262e6e8228d3346c441a /src/main/stanza/passes.stanza | |
| parent | c4271d9e428bba7b447ed6d18fb11729d2b61b22 (diff) | |
Standard Verilog doesn't use Resolve(), but lists out the resolution passes individually
Diffstat (limited to 'src/main/stanza/passes.stanza')
| -rw-r--r-- | src/main/stanza/passes.stanza | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 45aaf755..a5d72ba4 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -1642,8 +1642,11 @@ public defmethod name (b:Resolve) -> String : "Resolve" public defmethod short-name (b:Resolve) -> String : "resolve" defn resolve (c:Circuit) -> Circuit : + check-width $ infer-widths $ + check-genders $ resolve-genders $ + check-types $ infer-types $ resolve-kinds $ c |