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authorazidar2015-08-26 15:07:12 -0700
committerazidar2015-08-26 15:07:53 -0700
commitb6bf5ee9b29a117c1fcb3b7ec19ce1ce07132ffd (patch)
treec65e8d722c77fbbaa42c4b3d98e3d0ba6cdb9fca /src/main/stanza/passes.stanza
parentcf1fe102a99efee192288061849165072c699c2e (diff)
Fixed bug where firrtl was incorrectly judging the width of a bigint. #36 #37.
Diffstat (limited to 'src/main/stanza/passes.stanza')
-rw-r--r--src/main/stanza/passes.stanza4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 8a03fb10..fead9ac2 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -1983,14 +1983,14 @@ defn gen-constraints (m:Module, h:HashTable<Symbol,Type>, v:Vector<WGeq>) -> Mod
match(width(e)) :
(w:UnknownWidth) :
val w* = VarWidth(firrtl-gensym(`w,width-name-hash))
- add(v,WGeq(w*,LongWidth(max(1,num-bits(value(e)) - 1))))
+ add(v,WGeq(w*,LongWidth(max(1,req-num-bits(value(e)) - 1))))
UIntValue(value(e),w*)
(w) : e
(e:SIntValue) :
match(width(e)) :
(w:UnknownWidth) :
val w* = VarWidth(firrtl-gensym(`w,width-name-hash))
- add(v,WGeq(w*,LongWidth(num-bits(value(e)))))
+ add(v,WGeq(w*,LongWidth(req-num-bits(value(e)))))
SIntValue(value(e),w*)
(w) : e
(e) : e