WIP. Compiles, need to test

1 files changed, 221 insertions, 151 deletions

diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index dcd4c319..897bb94d 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -6,7 +6,6 @@ defpackage firrtl/passes :
   import firrtl/primops
   import firrtl-main
   ;import firrtl/errors
-  import firrtl/symbolic-value
   import bigint2
 
 ;============== Pass List ================
@@ -14,20 +13,20 @@ public val standard-passes = to-list $ [
    ;CheckHighForm()
    ;TempElimination()
    ToWorkingIR()
-   ;ResolveKinds()
+   ResolveKinds()
    ;CheckKinds()
-   ;InferTypes()
+   InferTypes()
    ;CheckTypes()
-   ;ResolveGenders()
+   ResolveGenders()
    ;CheckGenders()
    ;ExpandAccessors()
    ;LowerToGround()
-   ;;ExpandIndexedConnects()
+   ;ExpandIndexedConnects()
    ;InlineIndexed()
-   ;ExpandWhens()
-   ;InferWidths()
+   ExpandWhens()
+   InferWidths()
    ;Inline()
-   ;SplitExp()
+   SplitExp()
    ;CheckLowForm()
    ;ToRealIR() 
    ;Pad() 
@@ -40,7 +39,8 @@ public defstruct RegKind <: Kind
 public defstruct InstanceKind <: Kind
 public defstruct PortKind <: Kind
 public defstruct NodeKind <: Kind
-public defstruct MemKind <: Kind
+public defstruct MemKind <: Kind :
+   ports : List<Symbol>
 public defstruct ExpKind <: Kind
 
 public definterface Gender
@@ -204,7 +204,7 @@ var old-PRINT-GENDERS : True|False = false
 var old-PRINT-CIRCUITS : True|False = false
 var old-PRINT-DEBUG : True|False = false
 var old-PRINT-INFO : True|False = false
-public defn turn-off-debug () :
+defmethod turn-off-debug (x:False) :
    old-PRINT-TYPES = PRINT-TYPES
    old-PRINT-KINDS = PRINT-KINDS
    old-PRINT-WIDTHS = PRINT-WIDTHS
@@ -213,7 +213,7 @@ public defn turn-off-debug () :
    old-PRINT-CIRCUITS = PRINT-CIRCUITS
    old-PRINT-DEBUG = PRINT-DEBUG
    old-PRINT-INFO = PRINT-INFO
-public defn turn-on-debug () :
+defmethod turn-on-debug (x:False) :
    PRINT-TYPES = old-PRINT-TYPES
    PRINT-KINDS = old-PRINT-KINDS
    PRINT-WIDTHS = old-PRINT-WIDTHS
@@ -366,7 +366,7 @@ defn remove-unknowns-w (w:Width) -> Width :
    match(w) :
       (w:UnknownWidth) : VarWidth(firrtl-gensym(`w,width-name-hash))
       (w) : w
-defn remove-unknowns (t:Type) -> Type : mapr(remove-unknowns-w,t)
+defn remove-unknowns (t:Type) -> Type : t;mapr(remove-unknowns-w,t) TODO FIX!!!
 
 defmethod equal? (w1:Width,w2:Width) -> True|False :
    match(w1,w2) :
@@ -460,9 +460,9 @@ defn to-dir (g:Gender) -> Direction :
       MALE : INPUT
       FEMALE : OUTPUT
 defn to-gender (d:Direction) -> Gender :
-   switch {_ == g} :
+   switch {_ == d} :
       INPUT: MALE
-      OUPUT: FEMALE
+      OUTPUT: FEMALE
 
 ;================= Remove Special Characters ========================
 ; Returns a new Circuit where all names have all special characters 
@@ -646,7 +646,7 @@ defn resolve-kinds (c:Circuit) :
             (s:DefNode) : kinds[name(s)] = NodeKind()
             (s:DefRegister) : kinds[name(s)] = RegKind()
             (s:WDefInstance) : kinds[name(s)] = InstanceKind()
-            (s:DefMemory) : kinds[name(s)] = MemKind()
+            (s:DefMemory) : kinds[name(s)] = MemKind(append-all([readers(s) writers(s) readwriters(s)]))
             (s) : false
          map(find-stmt,s)
 
@@ -919,7 +919,7 @@ defn get-valid-points (t1:Type,t2:Type,flip1:Flip,flip2:Flip) -> List<[Int,Int]>
                add(points,[x[0] + i, x[1] + i])
          to-list(points)
 defn create-exps (n:Symbol, t:Type) -> List<Expression> :
-   create-exps(WRef(n,t,ExpKind(),UNKNOWN-GENDER)
+   create-exps(WRef(n,t,ExpKind(),UNKNOWN-GENDER))
 defn create-exps (e:WRef|WSubField|WSubIndex) -> List<Expression> :
    match(type(e)) : 
       (t:UIntType|SIntType|ClockType) : list(e)
@@ -995,7 +995,7 @@ defn expand-connects (c:Circuit) -> Circuit :
                (m:InModule) : expand-connects(m)
 
 
-;;================ REPLACE INDEXERS =========================
+;;;================ REPLACE INDEXERS =========================
 ; This pass inlines all accessors to non-memory vector typed
 ;   components.
 
@@ -1951,22 +1951,22 @@ defn split-exp (m:InModule) -> InModule :
    val sh = get-sym-hash(m,keys(v-keywords))
    defn split-exp-s (s:Stmt) -> Stmt :
       val base = match(s) :
-         (s:Connect) : get-name(loc(s))
+         (s:Connect) : lowered-name(loc(s))
          (s:DefNode) : name(s)
          (s:DefRegister) : name(s)
          (s) : `F
       defn split (e:Expression) -> Expression :
          val n = firrtl-gensym(base,sh)
          add(v,DefNode(info(s),n,e))
-         WRef(n,e,kind(e),type(e))
+         WRef(n,type(e),kind(e),gender(e))
       defn split-exp-e (e:Expression,i:Int) -> Expression :
          match(map(split-exp-e{_,i + 1},e)) :
             (e:DoPrim) :
-               if i > 0 : split(e,base)
+               if i > 0 : split(e)
                else : e
             (e) : e
-      map{split-exp{_,i},_} $ map(split-exp-s,s)
-   split-exp-s(body(m),v,sh)
+      map{split-exp-e{_,0},_} $ map(split-exp-s,s)
+   split-exp-s(body(m))
    InModule(info(m),name(m),ports(m),Begin(to-list(v)))
 
 defn split-exp (c:Circuit) -> Circuit :
@@ -2289,7 +2289,7 @@ public defn const-prop (c:Circuit) -> Circuit :
 ;         DoPrim(BITS-SELECT-OP,list(root-ref(e)),list(base,off),UIntType(IntWidth(off)))
 ;         
 ;;------------- Pass ------------------
-;
+
 ;defn condense-mems (m:InModule) -> InModule :
 ;   val mem-assigns = HashTable<Expression,Expression>(exp-hash)
 ;   defn collect-mems (s:Stmt) -> Stmt :
@@ -2344,14 +2344,49 @@ public defmethod name (b:LowerTypes) -> String : "Lower Types"
 public defmethod short-name (b:LowerTypes) -> String : "lower-types"
 
 ;------------- Utils ---------------
+defn is-ground? (t:Type) -> True|False :
+   match(t) :
+      (t:UIntType|SIntType) : true
+      (t) : false
+defn mport? (ex:Expression) -> True|False :
+   match(kind(ex)) :
+      (k:MemKind) : match(ex) : 
+         (ex:WRef|WSubIndex) : false
+         (ex:WSubField) :
+            var yes? = switch { _ == name(ex) } :
+                  `wdata : true
+                  `rdata : true
+                  `data : true
+                  `wmask : true
+                  else : false
+            yes? and match(exp(ex)) :
+               (e:WSubField) : 
+                  contains?(ports(kind(e) as MemKind),name(e)) and (exp(e) typeof WRef)
+               (e) : false
+         (ex) : false
+      (k) : false
+defn substitute (e:Expression, s:Symbol) -> Expression :
+   match(e) :
+      (e:WRef) : WRef(merge(name(e),s,`_),UnknownType(),kind(e),gender(e))
+      (e) : map(substitute{_,s},e)
+defn collect (e:Expression, s:Symbol) -> Expression :
+   match(e) :
+      (e:WSubField) : 
+         if mport?(exp(e)) : substitute(e,s)
+         else : collect(e,merge(name(e),s,`_))
+      (e:WSubIndex) : collect(e,merge(to-symbol(value(e)),s,`_))
+      (e) : e
+defn lower-mem (e:Expression) -> Expression :
+   match(e) :
+      (e:WSubField) : collect(exp(e),name(e))
+      (e:WSubIndex) : collect(exp(e),to-symbol(value(e)))
+      (e) : e
 
 defn merge (a:Symbol,b:Symbol,x:Symbol) -> Symbol : symbol-join([a x b])
 defn lowered-name (e:Expression) -> Symbol :
    match(e) :
       (e:WRef) : name(e)
-      (e:WSubField) : 
-         if kind(e) typeof MemKind|InstanceKind and exp(e) typeof WRef : name(e)
-         else : merge(lowered-name(exp(e)),name(e),`_)
+      (e:WSubField) : merge(lowered-name(exp(e)),name(e),`_)
       (e:WSubIndex) : merge(lowered-name(exp(e)),to-symbol(value(e)),`_)
 defn root-ref (e:Expression) -> Expression :
    match(e) :
@@ -2365,9 +2400,11 @@ defn lower-types (s:Stmt) -> Stmt :
       match(e) : 
          (e:WRef|UIntValue|SIntValue) : e
          (e:WSubField) : 
-            val root = root-ref(e)
-            match(kind(e)) 
-               (k:InstanceKind|MemKind) : WSubField(root,lowered-name(e),type(e),gender(e))
+            match(kind(e)) :
+               (k:InstanceKind) : 
+                  val temp = lowered-name(WRef(name(e),UnknownType(),InstanceKind(),MALE))
+                  WSubField(root-ref(e),temp,type(e),gender(e))
+               (k:MemKind) : lower-mem(e)
                (k) : WRef(lowered-name(e),type(e),kind(e),gender(e))
          (e:WSubIndex) : WRef(lowered-name(e),type(e),kind(e),gender(e))
          (e:DoPrim) : map(lower-types-e,e)
@@ -2378,24 +2415,22 @@ defn lower-types (s:Stmt) -> Stmt :
             val es = create-exps(name(s),type(s))
             Begin $ for e in es map :
                defn replace-type (t:Type) -> Type : type(e)
-               defn replace-name (n:Symbol) -> Symbol : name(e)
+               defn replace-name (n:Symbol) -> Symbol : lowered-name(e)
                map{replace-name,_} $ map(replace-type,s)
       (s:WDefInstance) :
          val fields* = for f in fields(type(s) as BundleType) map-append :
-            val es = create-exps(WRef(name(f),type(f),ExpKind(),flip(p) * MALE))
-            BundleType $ for e in es map :
+            val es = create-exps(WRef(name(f),type(f),ExpKind(),flip(f) * MALE))
+            for e in es map :
                switch { _ == gender(e) } :
-                  MALE : Field(name(e),DEFAULT,type(f))
-                  FEMALE : Field(name(e),REVERSE,type(f))
+                  MALE : Field(lowered-name(e),DEFAULT,type(f))
+                  FEMALE : Field(lowered-name(e),REVERSE,type(f))
          WDefInstance(info(s),name(s),module(s),BundleType(fields*))
       (s:DefMemory) :
-         if is
-         for f in fields(type(s) as BundleType) map-append :
-            val es = create-exps(WRef(name(f),type(f),ExpKind(),flip(p) * MALE))
-            BundleType $ for e in es map :
-               switch { _ == gender(e) } :
-                  MALE : Field(name(e),DEFAULT,type(f))
-                  FEMALE : Field(name(e),REVERSE,type(f))
+         if is-ground?(data-type(s)) : s
+         else :
+            val es = create-exps(name(s),data-type(s))
+            Begin $ for e in es map :
+               DefMemory(info(s),merge(name(s),lowered-name(e),`_),type(e),depth(s),write-latency(s),read-latency(s),readers(s),writers(s),readwriters(s))
       (s) : map(lower-types,s)
 
 defn lower-types (c:Circuit) -> Circuit :
@@ -2423,74 +2458,92 @@ defstruct VIndent
 defstruct VRandom
 val tab = VIndent()
 val ran = VRandom()
-defn get-width (t:Type) -> Long :
+defn escape (s:String) -> String :
+   val s* = Vector<String>()
+   add(s*,"\"");"
+   var percent = false
+   for c in s do :
+      if c == '\n' :
+         add(s*,"\\n")
+      else :
+         if c == 'x' and percent :
+            add(s*,"h")
+         else : add(s*,to-string(c))
+      percent = c == '%'
+   add(s*,"\"");"
+   string-join(s*)
+defn remove-root (ex:Expression) -> Expression :
+   match(exp(ex as WSubField)) :
+      (e:WSubField) : remove-root(e)
+      (e:WRef) : WRef(name(ex as WSubField),type(ex),InstanceKind(),UNKNOWN-GENDER)
+defn !empty? (s:Vector) -> True|False :
+   if length(s) == 0 : false
+   else : true
+defn long! (t:Type) -> Long :
    match(t) :
-      (t:UIntType|SIntType) : width(t)
+      (t:UIntType|SIntType) : width(width(t) as IntWidth)
       (t:BundleType) : 
-         var w = 0
-         for f in fields do :
-            w = w + get-width(type(f))
+         var w = to-long(0)
+         for f in fields(t) do :
+            w = w + long!(type(f))
          w
-      (t:VectorType) : size(t) * get-width(type(t))
-defn get-name (e:Expression) -> Symbol :
-   match(e) :
-      (e:WRef) : name(e)
-      (e:WSubField) : to-symbol $ string-join([get-name(exp(e)) `_ name(f)])
-      (e:WSubAccess) : print(e)
-      (e:WSubIndex) : print(e)
+      (t:VectorType) : to-long(size(t)) * long!(type(t))
    
-defn rand-string (t:Type) -> String : 
-   val w* = ((get-width(t) + to-long(31)) / to-long(32))
+defn rand-string (t:Type) -> Streamable : 
+   val w* = ((long!(t) + to-long(31)) / to-long(32))
    ["{" w* "{" ran "}};"]
-defn emit (s:Streamable, top:Int) :
-   for x in s do :
-      match(x) :
-         (e:Expression) :
-            turn-off-debug()
-            match(e) :
-               (e:DoPrim) : op-print(e)
-               (e:WRef) : print(e)
-               (e:WSubField) : print-all([exp(e) `_ name(f)])
-               (e:WSubAccess) : print(e)
-               (e:WSubIndex) : print(e)
-               (e:UIntValue|SIntValue) : v-print(e)
-            turn-on-debug()
-         (t:Type) :
-            match(t) :
-               (t:UIntType)
-         (s:Symbol) : print(s)
-         (i:Int) : print(i)
-         (s:String) : print(s)
-         (t:VIndent) : print("   ")
-         (r:VRandom) : print("$random")
-         (s:Streamable) : emit(s, top + 1)
-   if top == 0 : print("\n")
-
-
+defn emit (x:?) : emit(x,0)
+defn emit (x:?, top:Int) :
+   match(x) :
+      (e:Expression) :
+         turn-off-debug(false)
+         match(e) :
+            (e:DoPrim) : op-print(e)
+            (e:WRef) : print(e)
+            ;(e:WSubField) : print-all([exp(e) `_ name(f)])
+            (e:WSubAccess) : print(e)
+            (e:WSubIndex) : print(e)
+            (e:UIntValue|SIntValue) : v-print(e)
+         turn-on-debug(false)
+      (t:Type) :
+         match(t) :
+            (t:UIntType|SIntType) : 
+               val w = long!(t) - to-long(1)
+               if w >= to-long(0) : print-all(["[" w ":0]"])
+               else : ""
+      (s:Symbol) : print(s)
+      (i:Int) : print(i)
+      (s:String) : print(s)
+      (t:VIndent) : print("   ")
+      (r:VRandom) : print("$random")
+      (s:Streamable) : 
+         for x in s do :
+            emit(x, top + 1)
+         if top == 0 : print("\n")
 
 ;------------- PASS -----------------
 defn v-print (e:UIntValue|SIntValue) :
    val str = to-string(value(e))
    val out = substring(str,1,length(str) - 1)
    print $ string-join $ match(e) :
-      (e:UIntValue) : [width!(type(e)) "'" out]
-      (e:SIntValue) : [width!(type(e)) "'s" out]
-defn op-print (dprim:DoPrim) :
-   defn cast-if (e:Expression) -> String :
+      (e:UIntValue) : [long!(type(e)) "'" out]
+      (e:SIntValue) : [long!(type(e)) "'s" out]
+defn op-print (doprim:DoPrim) :
+   defn cast-if (e:Expression) -> ? :
       val signed? = for x in args(doprim) any? : type(x) typeof SIntType
       if not signed? : e
       else : match(type(e)) :
          (t:SIntType) : ["$signed(" e ")"]
          (t:UIntType) :  ["$signed({1'b0," e "})"]
-   defn cast (e:Expression) -> String
+   defn cast (e:Expression) -> ? :
       match(type(doprim)) :
          (t:UIntType) : e
          (t:SIntType) : ["$signed(" e ")"]
    defn a0 () -> Expression : args(doprim)[0]
    defn a1 () -> Expression : args(doprim)[1]
    defn a2 () -> Expression : args(doprim)[2]
-   defn c0 () -> Expression : consts(doprim)[0]
-   defn c1 () -> Expression : consts(doprim)[1]
+   defn c0 () -> Int : consts(doprim)[0]
+   defn c1 () -> Int : consts(doprim)[1]
 
    print $ string-join $ switch {_ == op(doprim)} :
       ADD-OP : [cast-if(a0()) " + " cast-if(a1())]
@@ -2512,12 +2565,12 @@ defn op-print (dprim:DoPrim) :
       EQUAL-OP : [cast-if(a0()) " == " cast-if(a1())]
       MUX-OP : [a0() " ? " cast(a1()) " : " cast(a2())]
       PAD-OP : 
-         val w = width!(type(a0()))
+         val w = long!(type(a0()))
          val diff = (to-long(c0()) - w)
          if w == to-long(0) : [ a0() ]
          else : match(type(doprim)) :
             (t:SIntType) : ["{{" diff "{" a0() "[" w - to-long(1) "]}}, " a0() " }"]
-            (t) : ["{{" diff "'d0 }, " x " }"]
+            (t) : ["{{" diff "'d0 }, " a0() " }"]
       AS-UINT-OP : ["$unsigned(" emit(a0()) ")"]
       AS-SINT-OP : ["$signed(" emit(a0()) ")"]
       DYN-SHIFT-LEFT-OP : [cast(a0()) " << " emit(a1())]
@@ -2526,7 +2579,7 @@ defn op-print (dprim:DoPrim) :
             (t:SIntType) : [cast(a0()) " >>> " a1()]
             (t) : [cast(a0()) " >> " a1()]
       SHIFT-LEFT-OP : [cast(a0()) " << " c0()]
-      SHIFT-RIGHT-OP : [cast(a0()) "[" width!(type(a0())) - to-long(1) ":" c0() "]"]
+      SHIFT-RIGHT-OP : [cast(a0()) "[" long!(type(a0())) - to-long(1) ":" c0() "]"]
       NEG-OP : ["-{" cast(a0()) "}"]
       CONVERT-OP : 
          match(type(a0())) :
@@ -2540,38 +2593,43 @@ defn op-print (dprim:DoPrim) :
       BIT-SELECT-OP : [cast(a0()) "[" c0() "]"]
       BITS-SELECT-OP : [cast(a0()) "[" c0() ":" c1() "]"]
       BIT-AND-REDUCE-OP : 
-         join{_," & "} $
-            for b in 0 to width!(type(doprim)) map :
-               [cast(a0() ) "[" b "]"]
+         val v = Vector<Streamable>()
+         for b in 0 to to-int(long!(type(doprim))) do :
+            add(v,[cast(a0()) "[" b "]"])
+         join(v," & ")
       BIT-OR-REDUCE-OP : 
-         join{_," | "} $
-            for b in 0 to width!(type(doprim)) map :
-               [cast(a0() ) "[" b "]"]
+         val v = Vector<Streamable>()
+         for b in 0 to to-int(long!(type(doprim))) do :
+            add(v,[cast(a0() ) "[" b "]"])
+         join(v," | ")
       BIT-XOR-REDUCE-OP : 
-         join{_," ^ "} $
-            for b in 0 to width!(type(doprim)) map :
-               [cast(a0() ) "[" b "]"]
+         val v = Vector<Streamable>()
+         for b in 0 to to-int(long!(type(doprim))) do :
+            add(v,[cast(a0() ) "[" b "]"])
+         join(v," ^ ")
 
 defn emit-verilog (m:InModule) -> Module :
    val netlist = HashTable<Expression,Expression>(exp-hash)
    val simlist = Vector<Stmt>()
+   val namehash = get-sym-hash(m,keys(v-keywords))
    defn build-netlist (s:Stmt) -> Stmt :
       match(s) :
          (s:Connect) : netlist[loc(s)] = exp(s)
          (s:Conditionally) : add(simlist,s)
          (s:DefNode) : 
-            val e = WRef(name(s),type(e),NodeKind(),MALE)
-            netlist[e] = exp(s)
+            val e = WRef(name(s),get-type(s),NodeKind(),MALE)
+            netlist[e] = value(s)
          (s) : map(build-netlist,s)
+      s
 
    val declares = Vector<Streamable>()
    val at-clock = HashTable<Expression,Vector<Streamable>>(exp-hash)
-   val initals = Vector<Streamable>()
+   val initials = Vector<Streamable>()
    val simulates = Vector<Streamable>()
    defn declare (b:Symbol,n:Symbol,t:Type) : 
       add(declares,[b t n ";"])
-   defn assign (e:Expression) : 
-      add(declares,["assign " e " = " netlist[e]])
+   defn assign (e:Expression,value:Expression) : 
+      add(declares,["assign " e " = " value])
    defn update-reset (e:Expression,clk:Expression,reset?:Expression,init:Expression) :
       add(at-clock[clk],["if(" reset? ") begin"])
       add(at-clock[clk],[tab e " <= " init])
@@ -2583,52 +2641,64 @@ defn emit-verilog (m:InModule) -> Module :
       add(at-clock[clk],[tab e " <= " netlist[e]])
       add(at-clock[clk],["end"])
    defn initialize (e:Expression) :
-      add(initals,[e " = " rand-string(type(e))])
+      add(initials,[e " = " rand-string(type(e))])
    defn initialize-mem (e:Expression,i:Int) :
-      add(initals,["for (initvar = 0; initvar < " i "; initvar = initvar+1)"])
+      add(initials,["for (initvar = 0; initvar < " i "; initvar = initvar+1)"])
       val index = WRef(`initvar,UnknownType(),ExpKind(),UNKNOWN-GENDER)
-      add(initals,[tab WSubAccess(e,index,UnknownType(),FEMALE), " = " rand-string(type(e))])
+      add(initials,[tab WSubAccess(e,index,UnknownType(),FEMALE), " = " rand-string(type(e))])
    defn instantiate (n:Symbol,m:Symbol,es:List<Expression>) :
       add(declares,[m " " n " ("])
       for (e in es,i in 1 to false) do :
-         val s = [tab "." remove-base(e) "(" netlist[e] ")"]
-         if i == size(es) : add(declares,[s ","])
+         val s = [tab "." remove-root(e) "(" netlist[e] ")"]
+         if i == length(es) : add(declares,[s ","])
          else : add(declares,s)
       add(declares,[");"])
    defn simulate (clk:Expression,en:Expression,s:Streamable) :
-      add(at-clock(clk),["`ifndef SYNTHESIS"])
-      add(at-clock(clk),[tab "if(" en ") begin"])
-      add(at-clock(clk),[tab tab s])
-      add(at-clock(clk),[tab "end"])
-      add(at-clock(clk),["`endif"])
+      add(at-clock[clk],["`ifndef SYNTHESIS"])
+      add(at-clock[clk],[tab "if(" en ") begin"])
+      add(at-clock[clk],[tab tab s])
+      add(at-clock[clk],[tab "end"])
+      add(at-clock[clk],["`endif"])
    defn stop (ret:Int) -> Streamable :
       ["$fdisplay(32/'h80000002," ret ");$finish;"]
    defn printf (str:String,args:List<Expression>) -> Streamable :
       val str* = join(List(escape(str),args),",")
       ["$fdisplay(32/'h80000002," str* ");"]
+   defn delay (e:Expression, n:Int) -> Expression :
+      var e* = e
+      for i in 0 to n do :
+         val name = firrtl-gensym(lowered-name(e),namehash)
+         declare(`reg,name,type(e))
+         val e** = WRef(name,type(e),ExpKind(),UNKNOWN-GENDER)
+         assign(e**,e*)
+         e* = e**
+      e*
+
    defn build-streams (s:Stmt) -> Stmt :
       match(s) :
          (s:DefWire) : 
             val es = create-exps(WRef(name(s),type(s),WireKind(),BI-GENDER))
             for e in es do : 
-               declare(`wire,get-name(e),type(e))
-               assign(e)
+               declare(`wire,lowered-name(e),type(e))
+               assign(e,netlist[e])
          (s:DefRegister) :
             val es = create-exps(WRef(name(s),type(s),RegKind(),BI-GENDER))
             for e in es do : 
-               declare(`reg,get-name(e),type(e))
-               update-reset(e,clk(s),reset(s),init(s))
+               declare(`reg,lowered-name(e),type(e))
+               update-reset(e,clock(s),reset(s),init(s))
                initialize(e)
          (s:DefPoison) :
             val es = create-exps(WRef(name(s),type(s),PoisonKind(),MALE))
             for e in es do :
-               declare(`wire,get-name(e),type(e))
+               declare(`wire,lowered-name(e),type(e))
                initialize(e)
          (s:DefNode) :
-            declare(`wire,name(s),type(exp(s)))
-            netlist[name(s)] = exp(s)
-            assign(WRef(name(s),type(exp(s)),NodeKind(),MALE))
+            declare(`wire,name(s),type(value(s)))
+            assign(WRef(name(s),type(value(s)),NodeKind(),MALE),value(s))
          (s:Conditionally) :
+            match(conseq(s)) :
+               (c:Stop) : simulate(clk(c),pred(s),stop(ret(c)))
+               (c:Print) : simulate(clk(c),pred(s),printf(string(c),args(c)))
          (s:Stop) : simulate(clk(s),one,stop(ret(s)))
          (s:Print) : simulate(clk(s),one,printf(string(s),args(s)))
          (s:WDefInstance) :
@@ -2636,47 +2706,46 @@ defn emit-verilog (m:InModule) -> Module :
             instantiate(name(s),module(s),es)
          (s:DefMemory) : ;TODO expand bundle in declaration, lots of thinking todo
             declare(`reg,name(s),VectorType(data-type(s),depth(s)))
-            val mem = WRef(name(s),type(s),MemKind(),BI-GENDER)
+            val mem = WRef(name(s),get-type(s),MemKind(append-all([readers(s) writers(s) readwriters(s)])),BI-GENDER)
             initialize-mem(mem,depth(s))
             
             for r in readers(s) do :
                val port = HashTable<Symbol,Expression>(symbol-hash)
-               for f in fields(type(s) as BundleType) do :
+               for f in fields(get-type(s) as BundleType) do :
                   port[name(f)] = WSubField(mem,name(f),type(f),UNKNOWN-GENDER)
-               val addr* = delay(port[`addr],read-latency)
-               val en* = delay(port[`en],read-latency)
-               val es = create-exps(port[`rdata])
-               for e in es do : 
-                  netlist[e] = WSubAccess(mem,addr*,type(port[`rdata]),FEMALE)
-                  update(e,port[`clk],en*)
+               val addr* = delay(port[`addr],read-latency(s))
+               val en* = delay(port[`en],read-latency(s))
+               val e = port[`rdata]
+               netlist[e] = WSubAccess(mem,addr*,type(port[`rdata]),FEMALE)
+               update(e,port[`clk],en*)
 
             for w in writers(s) do :
                val port = HashTable<Symbol,Expression>(symbol-hash)
-               for f in fields(type(s) as BundleType) do : 
-                  port[name(f)] = WSubField(mem,name(f),type(f),UNKNOWN)
-               val addr* = delay(port[`addr],write-latency - 1)
-               val en* = delay(port[`en],write-latency - 1)
-               val wmask* = delay(port[`wmask],write-latency - 1)
-               val es = create-exps(WSubAccess(port[`wdata],addr*,type(port[`wdata]),FEMALE))
-               for (e in es,m in create-exps(wmask*)) do :
-                  update(e,port[`clk],AND(en*,m))
+               for f in fields(get-type(s) as BundleType) do : 
+                  port[name(f)] = WSubField(mem,name(f),type(f),UNKNOWN-GENDER)
+               val addr* = delay(port[`addr],write-latency(s) - 1)
+               val en* = delay(port[`en],write-latency(s) - 1)
+               val wmask* = delay(port[`wmask],write-latency(s) - 1)
+               val e = WSubAccess(port[`wdata],addr*,type(port[`wdata]),FEMALE)
+               update(e,port[`clk],AND(en*,wmask*))
 
             for rw in readwriters(s) do :
                val port = HashTable<Symbol,Expression>(symbol-hash)
-               for f in fields(type(s) as BundleType) do :
+               for f in fields(get-type(s) as BundleType) do :
                   port[name(f)] = WSubField(mem,name(f),type(f),UNKNOWN-GENDER)
-               val raddr* = delay(port[`raddr],read-latency)
-               val ren* = delay(port[`ren],read-latency)
-               val res = create-exps(port[`rdata])
-               for e in res do : 
-                  netlist[e] = WSubAccess(mem,raddr*,type(port[`rdata]),FEMALE)
-                  update(e,port[`clk],ren*)
-               val waddr* = delay(port[`waddr],write-latency - 1)
-               val wen* = delay(port[`wen],write-latency - 1)
-               val wmask* = delay(port[`wmask],write-latency - 1)
-               val wes = create-exps(WSubAccess(port[`wdata],waddr*,type(port[`wdata]),FEMALE))
-               for (e in wes,m in create-exps(wmask*)) do : update(e,port[`clk],AND(wen*,m))
+               val raddr* = delay(port[`raddr],read-latency(s))
+               val ren* = delay(port[`ren],read-latency(s))
+               val re = port[`rdata]
+               netlist[re] = WSubAccess(mem,raddr*,type(port[`rdata]),FEMALE)
+               update(re,port[`clk],ren*)
+
+               val waddr* = delay(port[`waddr],write-latency(s) - 1)
+               val wen* = delay(port[`wen],write-latency(s) - 1)
+               val wmask* = delay(port[`wmask],write-latency(s) - 1)
+               val we = WSubAccess(port[`wdata],waddr*,type(port[`wdata]),FEMALE)
+               update(we,port[`clk],AND(wen*,wmask*))
          (s:Begin) : map(build-streams,s)
+      s
 
    defn emit-streams () :
       if !empty?(declares) :
@@ -2688,7 +2757,7 @@ defn emit-verilog (m:InModule) -> Module :
          emit(["  integer initvar;"])
          emit(["  initial begin"])
          emit(["    #0.002;"])
-         for x in initals do :
+         for x in initials do :
             emit([tab x])
          emit(["  end"])
          emit(["`endif"])
@@ -2703,6 +2772,7 @@ defn emit-verilog (m:InModule) -> Module :
    build-netlist(body(m))
    build-streams(body(m))
    emit-streams()
+   m
 
 defn emit-verilog (with-output:(() -> False) -> False, c:Circuit) :
    with-output $ fn () :