diff options
| author | azidar | 2016-02-06 09:59:13 -0800 |
|---|---|---|
| committer | azidar | 2016-02-09 18:57:07 -0800 |
| commit | 69597a7d57236bc43c964f7714bfa8ed53bf3bee (patch) | |
| tree | dd9d9870fe4fb2d21690d1757177fd10facfab99 /src/main/stanza/passes.stanza | |
| parent | bf900917c50a440632dbcaae17bcfe9613d14452 (diff) | |
Added constprop,v-wrap,v-rename. All set to attempt like->like comparison of rocketchip
Diffstat (limited to 'src/main/stanza/passes.stanza')
| -rw-r--r-- | src/main/stanza/passes.stanza | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 155c1b0a..9d7a1b97 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -2895,3 +2895,5 @@ defn lo-to-verilog (with-output:(() -> False) -> False, c:Circuit) : val c5 = verilog-rename(c4) ;println(c5) emit-verilog(with-output,c5) + + |