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authorazidar2016-01-26 14:16:09 -0800
committerazidar2016-01-28 09:25:03 -0800
commitf711861808e3ca914f71a3089c6879dbcb7dc08d (patch)
treed7864745eaa8048e6a0a2126c150102dd1b2c864 /src/main/stanza/ir-utils.stanza
parent6c2b6ea5e4ec00aae0963402e2565e91e95098ac (diff)
Changed register syntax for optional reset and init values
Diffstat (limited to 'src/main/stanza/ir-utils.stanza')
-rw-r--r--src/main/stanza/ir-utils.stanza3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index cf9e03e2..66e095fc 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -420,7 +420,8 @@ defmethod print (o:OutputStream, c:Stmt) :
(c:DefWire) :
print-all(o,["wire " name(c) " : " type(c)])
(c:DefRegister) :
- print-all(o,["reg " name(c) " : " type(c) ", " clock(c) ", " reset(c) ", " init(c)])
+ print-all(o,["reg " name(c) " : " type(c) ", " clock(c) " with :"])
+ print-all(io,["\nreset => (" reset(c) ", " init(c) ")"])
(c:DefMemory) :
print-all(o,["mem " name(c) " : "])
print-debug(o,c)