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authorazidar2015-12-03 15:12:02 -0800
committerazidar2016-01-16 14:28:17 -0800
commitc427b31a1ef8361b643d5f7435aeb42472dfe626 (patch)
tree6ae504ba1b37b9d0fef281b491cf932ac6826c7b /src/main/stanza/ir-utils.stanza
parentece8ec00868c182e141e8d1ac75bfb60bfaa87ec (diff)
WIP. Compiles and almost done with verilog backend. Need to think about emitting ports (and the assignments to them)
Diffstat (limited to 'src/main/stanza/ir-utils.stanza')
-rw-r--r--src/main/stanza/ir-utils.stanza8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index ba0e2423..4b70175a 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -9,9 +9,9 @@ defpackage firrtl/ir-utils :
public defmulti print-debug (o:OutputStream, e:Expression|Stmt|Type|Port|Field|Module|Circuit) -> False
public defmethod print-debug (o:OutputStream, e:Expression|Stmt|Type|Port|Field|Module|Circuit) -> False : false
public defmulti turn-off-debug (x:False) -> False
-public defmethod turn-off-debug (x:False) : false
+;public defmethod turn-off-debug (x:False) : false
public defmulti turn-on-debug (x:False)
-public defmethod turn-on-debug (x:False) : false
+;public defmethod turn-on-debug (x:False) : false
;============== GENSYM STUFF ======================
@@ -314,9 +314,9 @@ defmethod print (o:OutputStream, c:Stmt) :
(c:Begin) :
do(print{o,_}, join(body(c), "\n"))
(c:Connect) :
- print-all(o, [loc(c) " := " exp(c)])
+ print-all(o, [loc(c) " <= " exp(c)])
(c:BulkConnect) :
- print-all(o, [loc(c) " <> " exp(c)])
+ print-all(o, [loc(c) " <- " exp(c)])
(c:Empty) :
print(o, "skip")
(c:Stop) :