Added external modules. Switched lower firrtl back to wire r; r := Register, instead of using nodes. Added a renaming pass for different backends. This will likely get deprecated, as a more robust name mangling scheme could be needed

1 files changed, 13 insertions, 1 deletions

diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index 28cdd136..4271edca 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -18,6 +18,10 @@ public defn firrtl-gensym (s:Symbol) -> Symbol :
    
 public defn firrtl-gensym () -> Symbol :
    firrtl-gensym(`gen)
+
+;public defn get-sym-hash (m:Circuit) -> HashTable<Symbol,Int> :
+   ;public defn get-sym-hash (c:Circuit) -> HashTable<Symbol,Int> :
+   
    
 ;============== Exceptions =====================
 
@@ -183,7 +187,7 @@ defmethod print (o:OutputStream, p:Port) :
    print-all(o, [direction(p) " " name(p) " : " type(p)])
    print-debug(o,p)
 
-defmethod print (o:OutputStream, m:Module) :
+defmethod print (o:OutputStream, m:InModule) :
    print-all(o, ["module " name(m) " :"])
    print-debug(o,m)
    print(o,"\n")
@@ -192,6 +196,14 @@ defmethod print (o:OutputStream, m:Module) :
       println(io,p)
    print(io,body(m))
 
+defmethod print (o:OutputStream, m:ExModule) :
+   print-all(o, ["exmodule " name(m) " :"])
+   print-debug(o,m)
+   print(o,"\n")
+   val io = IndentedStream(o, 3)
+   for p in ports(m) do :
+      println(io,p)
+
 defmethod print (o:OutputStream, c:Circuit) :
    print-all(o, ["circuit " main(c) " :"])
    print-debug(o,c)