diff options
| author | jackbackrack | 2015-06-02 08:47:40 -0700 |
|---|---|---|
| committer | jackbackrack | 2015-06-02 08:47:40 -0700 |
| commit | b178ca42fd9d4f7b94d80c01cd810bf18da9ebc8 (patch) | |
| tree | 033e197aa2e297187e21712faf1957eb405b435b /src/main/stanza/ir-parser.stanza | |
| parent | e668a13b285c87678a708a8af5bee2cfa0f7645b (diff) | |
| parent | 8fc826a2770f46d63d8d7b1bccf14d2bf6e6b7cd (diff) | |
merge + fix trim to use correct bits operands
Diffstat (limited to 'src/main/stanza/ir-parser.stanza')
| -rw-r--r-- | src/main/stanza/ir-parser.stanza | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza index 0833543f..cbfe106e 100644 --- a/src/main/stanza/ir-parser.stanza +++ b/src/main/stanza/ir-parser.stanza @@ -151,9 +151,15 @@ defsyntax firrtl : module = (module ?name:#id! #:! (?ps:#port ... ?cs:#stmt ... ?rest ...)) : if not empty?(rest) : FPE(rest, "Expected a statement here.") - Module(first-info(form),name, ps, Begin(cs)) + InModule(first-info(form),name, ps, Begin(cs)) + module = (exmodule ?name:#id! #:! (?ps:#port ... ?rest ...)) : + if not empty?(rest) : + FPE(rest, "Expected a port here.") + ExModule(first-info(form),name, ps) module != (module) : FPE(form, "Invalid syntax for module definition.") + module != (exmodule) : + FPE(form, "Invalid syntax for exmodule definition.") defrule port : port = (input ?name:#id! #:! ?type:#type!) : Port(first-info(form),name, INPUT, type) @@ -187,13 +193,15 @@ defsyntax firrtl : defrule statements : stmt = (wire ?name:#id! #:! ?t:#type!) : DefWire(first-info(form),name, t) stmt = (reg ?name:#id! #:! ?t:#type!) : DefRegister(first-info(form),name, t) - stmt = (mem ?name:#id! #:! ?t:#vectype!) : DefMemory(first-info(form),name, t) + stmt = (cmem ?name:#id! #:! ?t:#vectype!) : DefMemory(first-info(form),name, t, false) + stmt = (smem ?name:#id! #:! ?t:#vectype!) : DefMemory(first-info(form),name, t, true) stmt = (inst ?name:#id! #of! ?m:#ref!) : DefInstance(first-info(form),name, m) stmt = (node ?name:#id! #=! ?e:#exp!) : DefNode(first-info(form),name, e) stmt = (accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name, s, i) stmt = (?s:#stmt/when) : s stmt = (?x:#exp := ?y:#exp!) : Connect(first-info(form),x, y) + stmt = (?x:#exp <> ?y:#exp!) : BulkConnect(first-info(form),x, y) stmt = (on-reset ?x:#exp := ?y:#exp!) : OnReset(first-info(form),x, y) stmt = ((?s:#stmt ?ss:#stmt ... ?rest ...)) : |