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authorazidar2016-01-24 16:30:50 -0800
committerazidar2016-01-24 16:30:50 -0800
commit8265e2e67e39f2d313a74bccb6dd45d85f706f3a (patch)
tree744a5eea0e86a43aaeb720fc545bcfe80840b139 /src/main/stanza/ir-parser.stanza
parent63b3668414bfea1c3bdd651a552d5fa7b5d6b9c4 (diff)
Added muxing on passive aggregate types
Diffstat (limited to 'src/main/stanza/ir-parser.stanza')
-rw-r--r--src/main/stanza/ir-parser.stanza4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index 7c457c19..5d5d56ec 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -76,7 +76,7 @@ OPERATORS[`eq] = EQUAL-OP
OPERATORS[`neq] = NEQUAL-OP
OPERATORS[`eqv] = EQUIV-OP
OPERATORS[`neqv] = NEQUIV-OP
-OPERATORS[`mux] = MUX-OP
+;OPERATORS[`mux] = MUX-OP
OPERATORS[`pad] = PAD-OP
OPERATORS[`neg] = NEG-OP
OPERATORS[`asUInt] = AS-UINT-OP
@@ -365,6 +365,8 @@ defsyntax firrtl :
val num-bits = req-num-bits(v as Int)
SIntValue(BigIntLit(v as Int,num-bits), IntWidth(num-bits))
+ expterm = (mux(?cond:#exp ?tval:#exp ?fval:#exp)) :
+ Mux(cond,tval,fval,UnknownType())
expterm = (?op:#sym(?es:#exp ... ?ints:#int ... ?rest ...)) :
if not empty?(rest) :
FPE(rest, "Illegal operands to primitive operator.")