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authorazidar2015-07-06 17:45:06 -0700
committerazidar2015-07-14 11:29:55 -0700
commit68f7ac42d01c88bcc0c77c919587618673658c76 (patch)
tree054c3a2fdb710b187664fb9e7212046f12ec2ef2 /src/main/stanza/ir-parser.stanza
parent8d6c83072cd60ecc376d81eb9a48ccf0f67e57f6 (diff)
Still partial commit, many tests pass. Many tests fail.
Diffstat (limited to 'src/main/stanza/ir-parser.stanza')
-rw-r--r--src/main/stanza/ir-parser.stanza17
1 files changed, 15 insertions, 2 deletions
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index 374cf58c..f85ff7c9 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -131,6 +131,10 @@ defsyntax firrtl :
FPE(form, "Expected a vector type here.") when t not-typeof VectorType
t
+ ;Error if not an accessor direction
+ accdir! = (?a:#accdir) : a
+ accdir! != () : FPE(form, "Expected an accessor direction here.")
+
;Error if not an expression
exp! = (?e:#exp) : e
exp! != () : FPE(form, "Expected an expression here.")
@@ -196,6 +200,12 @@ defsyntax firrtl :
field = (flip ?name:#id! #:! ?type:#type!) : Field(name, REVERSE, type)
field = (?name:#id #:! ?type:#type!) : Field(name, DEFAULT, type)
+ defrule accdir :
+ accdir = (read) : READ
+ accdir = (write) : WRITE
+ accdir = (infer) : INFER
+ accdir = (rdwr) : RDWR
+
defrule width :
width = (?x:#int) : IntWidth(x)
width = (?) : UnknownWidth()
@@ -208,12 +218,15 @@ defsyntax firrtl :
stmt = (smem ?name:#id! #:! ?t:#vectype!) : DefMemory(first-info(form),name, t, true)
stmt = (inst ?name:#id! #of! ?m:#ref!) : DefInstance(first-info(form),name, m)
stmt = (node ?name:#id! #=! ?e:#exp!) : DefNode(first-info(form),name, e)
- stmt = (accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name, s, i)
+ stmt = (on-reset ?x:#exp := ?y:#exp!) : OnReset(first-info(form),x, y)
+ stmt = (read accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name, s, i,READ)
+ stmt = (write accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name, s, i,WRITE)
+ stmt = (infer accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name, s, i,INFER)
+ stmt = (rdwr accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name, s, i,RDWR)
stmt = (?s:#stmt/when) : s
stmt = (?x:#exp := ?y:#exp!) : Connect(first-info(form),x, y)
stmt = (?x:#exp <> ?y:#exp!) : BulkConnect(first-info(form),x, y)
- stmt = (on-reset ?x:#exp := ?y:#exp!) : OnReset(first-info(form),x, y)
stmt = ((?s:#stmt ?ss:#stmt ... ?rest ...)) :
if not empty?(rest) :