diff options
| author | azidar | 2015-03-11 20:21:08 -0700 |
|---|---|---|
| committer | azidar | 2015-03-11 20:21:08 -0700 |
| commit | dbd3a844953fb8630f8b2ca5706c764533b661b0 (patch) | |
| tree | ee62f7a1ade1f15b2ca4069b7705ac44a4ba7a2e /src/main/stanza/ir-parser.stanza | |
| parent | 70e1a41b15632afd969fff7ed6100eba0be78297 (diff) | |
Finished expand accessors pass. Fixed bug in resolve-gender. Added tests, all pass. Minimal removal of letrec to get WritePort to work correctly - a more thorough removeal is still needed
Diffstat (limited to 'src/main/stanza/ir-parser.stanza')
| -rw-r--r-- | src/main/stanza/ir-parser.stanza | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza index 0334bca2..a9ea7c30 100644 --- a/src/main/stanza/ir-parser.stanza +++ b/src/main/stanza/ir-parser.stanza @@ -146,10 +146,6 @@ rd.defsyntax firrtl : defrule element : (reg ?name:#symbol : ?type:#type = Register (@do ?value:#exp ?en:#exp)) : ut(name) => Register(type, value, en) - (mem ?name:#symbol : ?type:#type = Memory - (@do (?i:#exp => WritePort (@do ?value:#exp ?en:#exp) @...))) : - val ports = map(WritePort, i, value, en) - ut(name) => Memory(type, ports) (node ?name:#symbol : ?type:#type = ?exp:#exp) : ut(name) => Node(type, exp) (inst ?name:#symbol = Instance (@do ?module:#exp @@ -271,8 +267,10 @@ rd.defsyntax firrtl : SIntValue(ut(value), IntWidth(ut(width))) (SInt (@do ?value:#int)) : SIntValue(ut(value), UnknownWidth()) - (ReadPort (@do ?mem:#exp ?index:#exp)) : - ReadPort(mem, index, UnknownType()) + (WritePort (@do ?mem:#exp ?index:#exp ?enable:#exp)) : + WritePort(mem, index, UnknownType(), enable) + (ReadPort (@do ?mem:#exp ?index:#exp ?enable:#exp)) : + ReadPort(mem, index, UnknownType(), enable) (?op:#symbol (@do ?es:#exp ... ?ints:#int ...)) : match(get?(operators, ut(op), false)) : (op:PrimOp) : |