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| author | azidar | 2015-04-09 16:57:00 -0700 |
|---|---|---|
| committer | azidar | 2015-04-09 16:57:00 -0700 |
| commit | a604e0789a85d8b3c5d6def2f9860047f479b68a (patch) | |
| tree | ff2890d273f30155c52b610824a3ea632f2c12c6 /src/main/stanza/ir-parser.stanza | |
| parent | 16b9cb55c7d3e546af7eee3528079c9ac9bb530b (diff) | |
Added more 'fake' tests. infer-widths now collects constraints
Diffstat (limited to 'src/main/stanza/ir-parser.stanza')
| -rw-r--r-- | src/main/stanza/ir-parser.stanza | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza index 8f0cc8e3..87458185 100644 --- a/src/main/stanza/ir-parser.stanza +++ b/src/main/stanza/ir-parser.stanza @@ -259,6 +259,8 @@ rd.defsyntax firrtl : WritePort(mem, index, UnknownType(), enable) (ReadPort (@do ?mem:#exp ?index:#exp ?enable:#exp)) : ReadPort(mem, index, UnknownType(), enable) + (Register (@do ?value:#exp ?enable:#exp)) : + Register(UnknownType(),value,enable) (?op:#symbol (@do ?es:#exp ... ?ints:#int ...)) : println("Op-symbol is:~" % [op]) match(get?(operators, ut(op), false)) : |