diff options
| author | azidar | 2015-06-04 14:56:18 -0700 |
|---|---|---|
| committer | azidar | 2015-06-04 14:56:18 -0700 |
| commit | 06f57fefe8258c7d8149156db7ca01a66f207a5d (patch) | |
| tree | 2598d83574f3675e42e763c18fbb6793b779c8df /src/main/stanza/flo.stanza | |
| parent | d86272ca9238c12e80e78938bc1dd5a1dc8532da (diff) | |
Fixed fir files so they correctly compile to verilog! Front-end needs to generate as-SInt instead of convert, always. Added fast build to Makefile
Diffstat (limited to 'src/main/stanza/flo.stanza')
| -rw-r--r-- | src/main/stanza/flo.stanza | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza index 22b0c978..fd000e20 100644 --- a/src/main/stanza/flo.stanza +++ b/src/main/stanza/flo.stanza @@ -89,7 +89,7 @@ public defn pad-widths (c:Circuit) -> Circuit : Circuit{info(c),_,main(c)} $ for m in modules(c) map : match(m) : - (m:ExModule) : error("Cannot use flo backend with external modules") + (m:ExModule) : m (m:InModule) : InModule(info(m),name(m),ports(m),pad-widths-s(body(m))) ;============= Flo Backend ================ |