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authorazidar2015-07-06 17:45:06 -0700
committerazidar2015-07-06 17:45:06 -0700
commitd9ece539b630ef9988f6f6e2159b5126e1728ccd (patch)
tree5cd7797623e4eb35e48c9fcfdc8475e4b93bce51 /src/main/stanza/flo.stanza
parent3145eaab41e76cc8cd18ceea01d7548fa539f1b6 (diff)
Still partial commit, many tests pass. Many tests fail.
Diffstat (limited to 'src/main/stanza/flo.stanza')
-rw-r--r--src/main/stanza/flo.stanza87
1 files changed, 0 insertions, 87 deletions
diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza
index fd000e20..cf15638d 100644
--- a/src/main/stanza/flo.stanza
+++ b/src/main/stanza/flo.stanza
@@ -5,93 +5,6 @@ defpackage firrtl/flo :
import firrtl/ir2
import firrtl/passes
-;========== Pad Widths ==================
-
-public defstruct Pad <: Pass
-public defmethod pass (b:Pad) -> (Circuit -> Circuit) : pad-widths
-public defmethod name (b:Pad) -> String : "Pad Widths"
-
-defn int-width! (t:Type) -> Int :
- match(width!(t)) :
- (w:IntWidth) : width(w)
- (w) : error("Non-int width")
-
-defn set-width (desired:Int,t:Type) -> Type :
- match(t) :
- (t:UIntType) : UIntType(IntWidth(desired))
- (t:SIntType) : SIntType(IntWidth(desired))
- (t) : error("Non-ground type")
-
-defn pad-widths-e (desired:Int,e:Expression) -> Expression :
- defn trim (desired:Int, e:Expression) :
- ;; println-all(["TRIM " desired " e " e])
- DoPrim(BITS-SELECT-OP,list(e),list(desired - 1, 0),set-width(desired,type(e)))
- defn pad (desired:Int, e:Expression) :
- ;; println-all(["PAD " desired " e " e])
- DoPrim(PAD-OP,list(e),list(desired),set-width(desired,type(e)))
- defn trim-pad (desired:Int, e:Expression) :
- val i = int-width!(type(e))
- if i > desired : trim(desired, e)
- else if i == desired : e
- else : pad(desired, e)
- defn self-pad-widths-e (e:Expression) -> Expression :
- pad-widths-e(int-width!(type(e)), e)
- ;; println-all(["PAD-E " desired " " e])
- match(e) :
- (e:DoPrim) :
- val new-desired = reduce(max, 0, map(int-width!{type(_)}, args(e)))
- ;; println-all([" NEW DESIRED " new-desired])
- val e* =
- if contains?([CONCAT-OP, DYN-SHIFT-RIGHT-OP, DYN-SHIFT-LEFT-OP], op(e)) :
- DoPrim(op(e), map(self-pad-widths-e, args(e)), consts(e), type(e))
- else if contains?([MUX-OP], op(e)) :
- DoPrim(op(e), list(pad-widths-e(1, args(e)[0]), pad-widths-e(new-desired, args(e)[1]), pad-widths-e(new-desired, args(e)[2])), consts(e), type(e))
- else :
- map(pad-widths-e{new-desired,_},e)
- trim-pad(desired, e*)
- (e:WRef|WSubfield|WIndex) :
- trim-pad(desired, e)
- (e:UIntValue) :
- val i = int-width!(type(e))
- if i > desired : trim(desired, e)
- else : UIntValue(value(e),IntWidth(desired))
- (e:SIntValue) :
- val i = int-width!(type(e))
- if i > desired : trim(desired, e)
- else : SIntValue(value(e),IntWidth(desired))
- (e:Register) :
- val value* = pad-widths-e(desired, value(e))
- Register(type(value*), value*, pad-widths-e(1, enable(e)))
- (e:ReadPort) :
- if int-width!(type(e)) != desired : error("ReadPort has different width than desired")
- else : ReadPort(mem(e), self-pad-widths-e(index(e)), type(e), pad-widths-e(1, enable(e)))
- (e:WritePort) :
- if int-width!(type(e)) != desired : error("WritePort has different width than desired")
- else : WritePort(mem(e), self-pad-widths-e(index(e)), type(e), pad-widths-e(1, enable(e)))
- (e) : error(to-string $ e)
-
-defn pad-widths-s (s:Stmt) -> Stmt :
- ;; println-all(["PAD-S " s])
- match(map(pad-widths-s,s)) :
- (s:Connect) :
- val i = int-width!(type(loc(s)))
- val loc* = pad-widths-e(i,loc(s))
- val exp* = pad-widths-e(i,exp(s))
- Connect(info(s),loc*,exp*)
- (s:DefNode) :
- val i = int-width!(type(value(s)))
- val exp* = pad-widths-e(i,value(s))
- DefNode(info(s),name(s),exp*)
- (s) :
- s
-
-public defn pad-widths (c:Circuit) -> Circuit :
- Circuit{info(c),_,main(c)} $
- for m in modules(c) map :
- match(m) :
- (m:ExModule) : m
- (m:InModule) : InModule(info(m),name(m),ports(m),pad-widths-s(body(m)))
-
;============= Flo Backend ================
public defstruct Flo <: Pass :