diff options
| author | azidar | 2015-07-06 17:45:06 -0700 |
|---|---|---|
| committer | azidar | 2015-07-06 17:45:06 -0700 |
| commit | d9ece539b630ef9988f6f6e2159b5126e1728ccd (patch) | |
| tree | 5cd7797623e4eb35e48c9fcfdc8475e4b93bce51 /src/main/stanza/firrtl-test-main.stanza | |
| parent | 3145eaab41e76cc8cd18ceea01d7548fa539f1b6 (diff) | |
Still partial commit, many tests pass. Many tests fail.
Diffstat (limited to 'src/main/stanza/firrtl-test-main.stanza')
| -rw-r--r-- | src/main/stanza/firrtl-test-main.stanza | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza index beb288b1..374fe438 100644 --- a/src/main/stanza/firrtl-test-main.stanza +++ b/src/main/stanza/firrtl-test-main.stanza @@ -11,7 +11,7 @@ #include("primop.stanza") #include("errors.stanza") #include("compilers.stanza") -#include("flo.stanza") +;#include("flo.stanza") #include("verilog.stanza") ;Custom Packages @@ -80,7 +80,8 @@ defn main () : run-passes(c,get-passes(to-list(pass-names))) else : switch {_ == compiler} : - "flo" : run-passes(c,StandardFlo(output as String)) + ;"flo" : run-passes(c,StandardFlo(output as String)) + "flo" : run-passes(c,StandardVerilog(output as String)) "verilog" : run-passes(c,StandardVerilog(output as String)) "verilute" : run-passes(c,InstrumentedVerilog(output as String,to-list $ pass-args)) else : error("Invalid compiler flag") |