First pass at a Verilog Backend. Not tested, but compiles and generates reasonable verilog. Requires inlining, future versions will instantiate modules

1 files changed, 2 insertions, 0 deletions

diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza
index 1b15c6b1..5a7e593d 100644
--- a/src/main/stanza/firrtl-test-main.stanza
+++ b/src/main/stanza/firrtl-test-main.stanza
@@ -11,6 +11,7 @@
 #include("errors.stanza")
 #include("compilers.stanza")
 #include("flo.stanza")
+#include("verilog.stanza")
 
 defpackage firrtl-main :
    import core
@@ -70,6 +71,7 @@ defn main () :
    else :
       switch {_ == compiler} :
          "flo" : run-passes(c,StandardFlo(output as String))
+         "verilog" : run-passes(c,StandardVerilog(output as String))
          else : error("Invalid compiler flag")
 
 main()