diff options
| author | azidar | 2015-07-07 14:56:47 -0700 |
|---|---|---|
| committer | azidar | 2015-07-14 11:29:55 -0700 |
| commit | 0d63d521de85d1c6b9109e019101d0f575d063f7 (patch) | |
| tree | db0db7ac3e5714464b4839e8b33ee37c45bd8518 /src/main/stanza/firrtl-test-main.stanza | |
| parent | 1c3b45cc4647feb504dace2f453d9306a1ea3325 (diff) | |
Updated flo backend
Diffstat (limited to 'src/main/stanza/firrtl-test-main.stanza')
| -rw-r--r-- | src/main/stanza/firrtl-test-main.stanza | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza index 374fe438..beb288b1 100644 --- a/src/main/stanza/firrtl-test-main.stanza +++ b/src/main/stanza/firrtl-test-main.stanza @@ -11,7 +11,7 @@ #include("primop.stanza") #include("errors.stanza") #include("compilers.stanza") -;#include("flo.stanza") +#include("flo.stanza") #include("verilog.stanza") ;Custom Packages @@ -80,8 +80,7 @@ defn main () : run-passes(c,get-passes(to-list(pass-names))) else : switch {_ == compiler} : - ;"flo" : run-passes(c,StandardFlo(output as String)) - "flo" : run-passes(c,StandardVerilog(output as String)) + "flo" : run-passes(c,StandardFlo(output as String)) "verilog" : run-passes(c,StandardVerilog(output as String)) "verilute" : run-passes(c,InstrumentedVerilog(output as String,to-list $ pass-args)) else : error("Invalid compiler flag") |