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authorazidar2015-04-09 16:57:00 -0700
committerazidar2015-04-09 16:57:00 -0700
commita604e0789a85d8b3c5d6def2f9860047f479b68a (patch)
treeff2890d273f30155c52b610824a3ea632f2c12c6 /src/main/stanza/firrtl-ir.stanza
parent16b9cb55c7d3e546af7eee3528079c9ac9bb530b (diff)
Added more 'fake' tests. infer-widths now collects constraints
Diffstat (limited to 'src/main/stanza/firrtl-ir.stanza')
-rw-r--r--src/main/stanza/firrtl-ir.stanza14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza
index 977c8ca1..f10dba0c 100644
--- a/src/main/stanza/firrtl-ir.stanza
+++ b/src/main/stanza/firrtl-ir.stanza
@@ -153,19 +153,19 @@ public defstruct Register <: Expression :
enable: Expression
public definterface Stmt
-public defstruct DefWire <: Stmt :
+public defstruct DefWire <: Stmt : ;LOW
name: Symbol
type: Type
public defstruct DefRegister <: Stmt :
name: Symbol
type: Type
-public defstruct DefInstance <: Stmt :
+public defstruct DefInstance <: Stmt : ;LOW
name: Symbol
module: Expression
-public defstruct DefMemory <: Stmt :
+public defstruct DefMemory <: Stmt : ;LOW
name: Symbol
type: VectorType
-public defstruct DefNode <: Stmt :
+public defstruct DefNode <: Stmt : ;LOW
name: Symbol
value: Expression
public defstruct DefAccessor <: Stmt :
@@ -176,12 +176,12 @@ public defstruct Conditionally <: Stmt :
pred: Expression
conseq: Stmt
alt: Stmt
-public defstruct Begin <: Stmt :
+public defstruct Begin <: Stmt : ;LOW
body: List<Stmt>
-public defstruct Connect <: Stmt :
+public defstruct Connect <: Stmt : ;LOW
loc: Expression
exp: Expression
-public defstruct EmptyStmt <: Stmt
+public defstruct EmptyStmt <: Stmt ;LOW
public definterface Type
public defstruct UIntType <: Type :