WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadblock in assigning clocked ports

1 files changed, 20 insertions, 0 deletions

diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza
index 7ac72922..8aba5f9c 100644
--- a/src/main/stanza/firrtl-ir.stanza
+++ b/src/main/stanza/firrtl-ir.stanza
@@ -160,6 +160,26 @@ public defstruct Print <: Stmt : ;LOW
    en: Expression
 public defstruct Empty <: Stmt ;LOW
 
+
+; CHIRRTL Features
+public defstruct MPortDir
+public val MRead = MPortDir()
+public val MWrite = MPortDir()
+public val MReadWrite = MPortDir()
+   
+public defstruct CDefMemory <: Stmt : ;LOW
+   info: FileInfo with: (as-method => true)
+   name: Symbol
+   type: Type
+   seq?: True|False
+public defstruct CDefMPort <: Stmt :
+   info: FileInfo with: (as-method => true)
+   name: Symbol
+   mem: Symbol
+   index: Expression
+   clk: Expression
+   direction: MPortDir
+
 public definterface Type
 public defstruct UIntType <: Type :
    width: Width