Removed IntWidth, now only use LongWidth. Now do width inference for Constants in parser, and correctly subtract 1 (except when 0) when calculating width from num-bits of BigInt

1 files changed, 6 insertions, 6 deletions

diff --git a/src/main/stanza/custom-passes.stanza b/src/main/stanza/custom-passes.stanza
index 44eb6b5e..ed71784d 100644
--- a/src/main/stanza/custom-passes.stanza
+++ b/src/main/stanza/custom-passes.stanza
@@ -45,7 +45,7 @@ defn when-coverage (port-name:Symbol, reg-name:Symbol, instrument?:HashTable<Sym
    val when-bits = Vector<Ref>()
    val inst-bits = Vector<Ref>()
    val sym = HashTable<Symbol,Int>(symbol-hash)
-   val w1 = IntWidth(1)
+   val w1 = LongWidth(1)
    val t1 = UIntType(w1)
    val u1 = UIntValue(BigIntLit("h1"),w1)
    defn when-coverage (s:Stmt) -> Stmt :
@@ -70,13 +70,13 @@ defn when-coverage (port-name:Symbol, reg-name:Symbol, instrument?:HashTable<Sym
 
    val w-ls = to-list $ when-bits
    if length(w-ls) != 0 :
-      val reg-ref = Ref(reg-name,UIntType(IntWidth(length(w-ls))))
+      val reg-ref = Ref(reg-name,UIntType(LongWidth(length(w-ls))))
       ;add{logic,_} $ DefRegister(FileInfo(),name(reg-ref),type(reg-ref)) TODO add clock and reset
       for (x in w-ls, i in 0 to false) do :
          add{logic,_} $ DefWire(FileInfo(),name(x),type(x))
          add{logic,_} $ Connect(FileInfo(),x,DoPrim(BIT-SELECT-OP,list(reg-ref),list(i),UIntType(w1)))
       add{logic,_} $ Connect(FileInfo(),reg-ref,concat-all(w-ls))
-      add{logic,_} $ OnReset(FileInfo(),reg-ref,UIntValue(BigIntLit("h0"),IntWidth(length(w-ls))))
+      add{logic,_} $ OnReset(FileInfo(),reg-ref,UIntValue(BigIntLit("h0"),LongWidth(length(w-ls))))
 
    val i-ls = to-list $ inst-bits
    if length(i-ls) != 0 :
@@ -161,7 +161,7 @@ public defn when-coverage (port-name:String, reg-name:String, c:Circuit) :
 ;   val when-bits = Vector<Ref>()
 ;   val inst-bits = Vector<Ref>()
 ;   val sym = HashTable<Symbol,Int>(symbol-hash)
-;   val w1 = IntWidth(1)
+;   val w1 = LongWidth(1)
 ;   val t1 = UIntType(w1)
 ;   val u1 = UIntValue(to-long $ 1,w1)
 ;   defn insert-temporal-asserts (s:Stmt) -> Stmt :
@@ -186,9 +186,9 @@ public defn when-coverage (port-name:String, reg-name:String, c:Circuit) :
 ;
 ;   val w-ls = to-list $ when-bits
 ;   if length(w-ls) != 0 :
-;      val reg-ref = Ref(reg-name,UIntType(IntWidth(length(w-ls))))
+;      val reg-ref = Ref(reg-name,UIntType(LongWidth(length(w-ls))))
 ;      add{logic,_} $ DefRegister(FileInfo(),name(reg-ref),type(reg-ref))
-;      add{logic,_} $ OnReset(FileInfo(),reg-ref,UIntValue(to-long $ 0,IntWidth(length(w-ls))))
+;      add{logic,_} $ OnReset(FileInfo(),reg-ref,UIntValue(to-long $ 0,LongWidth(length(w-ls))))
 ;      for (x in w-ls, i in 0 to false) do :
 ;         add{logic,_} $ DefWire(FileInfo(),name(x),type(x))
 ;         add{logic,_} $ Connect(FileInfo(),x,DoPrim(BIT-SELECT-OP,list(reg-ref),list(i),UIntType(w1)))