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| author | azidar | 2015-07-10 13:25:21 -0700 |
|---|---|---|
| committer | azidar | 2015-07-14 11:29:55 -0700 |
| commit | 0bfb3618b654a4082cc2780887b3ca32e374f455 (patch) | |
| tree | 230b7cbc96589be229e6f3d87f21300fb8fd84c3 /src/main/stanza/custom-passes.stanza | |
| parent | 0d63d521de85d1c6b9109e019101d0f575d063f7 (diff) | |
Added clock support
Diffstat (limited to 'src/main/stanza/custom-passes.stanza')
| -rw-r--r-- | src/main/stanza/custom-passes.stanza | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/stanza/custom-passes.stanza b/src/main/stanza/custom-passes.stanza index 6c1e58f6..4904d6d1 100644 --- a/src/main/stanza/custom-passes.stanza +++ b/src/main/stanza/custom-passes.stanza @@ -70,7 +70,7 @@ defn when-coverage (port-name:Symbol, reg-name:Symbol, instrument?:HashTable<Sym val w-ls = to-list $ when-bits if length(w-ls) != 0 : val reg-ref = Ref(reg-name,UIntType(IntWidth(length(w-ls)))) - add{logic,_} $ DefRegister(FileInfo(),name(reg-ref),type(reg-ref)) + ;add{logic,_} $ DefRegister(FileInfo(),name(reg-ref),type(reg-ref)) TODO add clock and reset add{logic,_} $ OnReset(FileInfo(),reg-ref,UIntValue(to-long $ 0,IntWidth(length(w-ls)))) for (x in w-ls, i in 0 to false) do : add{logic,_} $ DefWire(FileInfo(),name(x),type(x)) |