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authorazidar2015-08-24 11:47:02 -0700
committerazidar2015-08-24 11:47:02 -0700
commitb2be9c1bec800422581e208b22be9dffd6d0d5f1 (patch)
treedb3d41f281a63b85321c0e1930572f122ba900b4 /src/main/stanza/custom-passes.stanza
parent5d3061bfed8445370e6fa97ec9238ba49e8fafbc (diff)
Added BigInt error if passed a string without starting with a b or h
Diffstat (limited to 'src/main/stanza/custom-passes.stanza')
-rw-r--r--src/main/stanza/custom-passes.stanza6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/main/stanza/custom-passes.stanza b/src/main/stanza/custom-passes.stanza
index 30f0b6c5..44eb6b5e 100644
--- a/src/main/stanza/custom-passes.stanza
+++ b/src/main/stanza/custom-passes.stanza
@@ -47,7 +47,7 @@ defn when-coverage (port-name:Symbol, reg-name:Symbol, instrument?:HashTable<Sym
val sym = HashTable<Symbol,Int>(symbol-hash)
val w1 = IntWidth(1)
val t1 = UIntType(w1)
- val u1 = UIntValue(BigIntLit("1"),w1)
+ val u1 = UIntValue(BigIntLit("h1"),w1)
defn when-coverage (s:Stmt) -> Stmt :
match(s) :
(s:Conditionally) :
@@ -72,17 +72,17 @@ defn when-coverage (port-name:Symbol, reg-name:Symbol, instrument?:HashTable<Sym
if length(w-ls) != 0 :
val reg-ref = Ref(reg-name,UIntType(IntWidth(length(w-ls))))
;add{logic,_} $ DefRegister(FileInfo(),name(reg-ref),type(reg-ref)) TODO add clock and reset
- add{logic,_} $ OnReset(FileInfo(),reg-ref,UIntValue(BigIntLit("0"),IntWidth(length(w-ls))))
for (x in w-ls, i in 0 to false) do :
add{logic,_} $ DefWire(FileInfo(),name(x),type(x))
add{logic,_} $ Connect(FileInfo(),x,DoPrim(BIT-SELECT-OP,list(reg-ref),list(i),UIntType(w1)))
add{logic,_} $ Connect(FileInfo(),reg-ref,concat-all(w-ls))
+ add{logic,_} $ OnReset(FileInfo(),reg-ref,UIntValue(BigIntLit("h0"),IntWidth(length(w-ls))))
val i-ls = to-list $ inst-bits
if length(i-ls) != 0 :
for (x in i-ls, i in 0 to false) do :
add{logic,_} $ DefWire(FileInfo(),name(x),type(x))
- add{logic,_} $ Connect(FileInfo(),x,UIntValue(BigIntLit("0"),UnknownWidth()))
+ add{logic,_} $ Connect(FileInfo(),x,UIntValue(BigIntLit("h0"),UnknownWidth()))
if instrument?[name(m)] : add{logic,_} $ Connect(FileInfo(),port-ref,concat-all(append(w-ls,i-ls)))