diff options
| author | azidar | 2015-07-13 16:22:43 -0700 |
|---|---|---|
| committer | azidar | 2015-07-14 11:29:55 -0700 |
| commit | 271e1bf5ed56847c1ce7d50bdb7f1db9ccc5ea55 (patch) | |
| tree | 8b1cdfcfc97a9710bd1bc5be973578f712cfa253 /src/main/stanza/custom-compiler.stanza | |
| parent | 0bfb3618b654a4082cc2780887b3ca32e374f455 (diff) | |
Added tests for clocks. Added remove scope and special chars passes. Added tests. Made more tests pass
Diffstat (limited to 'src/main/stanza/custom-compiler.stanza')
| -rw-r--r-- | src/main/stanza/custom-compiler.stanza | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/main/stanza/custom-compiler.stanza b/src/main/stanza/custom-compiler.stanza index 91732f22..4d63a173 100644 --- a/src/main/stanza/custom-compiler.stanza +++ b/src/main/stanza/custom-compiler.stanza @@ -14,7 +14,9 @@ public defstruct InstrumentedVerilog <: Compiler : public defmethod passes (c:InstrumentedVerilog) -> List<Pass> : to-list $ [ WhenCoverage(args(c)[0],args(c)[1]) - CheckHighForm(expand-delin) + RemoveSpecialChars() + RemoveScopes() + CheckHighForm() TempElimination() ToWorkingIR() ;; MakeExplicitReset() @@ -31,8 +33,8 @@ public defmethod passes (c:InstrumentedVerilog) -> List<Pass> : InferWidths() SplitExp() ToRealIR() - SpecialRename(`#,`_) - CheckHighForm(expand-delin) + RemoveSpecialChars() + CheckHighForm() CheckLowForm() Verilog(file(c)) ] |