diff options
| author | azidar | 2015-07-30 18:26:40 -0700 |
|---|---|---|
| committer | azidar | 2015-07-30 18:26:40 -0700 |
| commit | 2440b824c68e4604d174e92e26af2c3eca1ec171 (patch) | |
| tree | da4417c923631571cb4247f351f17bfb7739f13d /src/main/stanza/custom-compiler.stanza | |
| parent | 30d3b50982a40eefeb5a2abcc8d85da1af88d84f (diff) | |
Added module name to error messages.
Diffstat (limited to 'src/main/stanza/custom-compiler.stanza')
| -rw-r--r-- | src/main/stanza/custom-compiler.stanza | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/stanza/custom-compiler.stanza b/src/main/stanza/custom-compiler.stanza index 4d63a173..85275c94 100644 --- a/src/main/stanza/custom-compiler.stanza +++ b/src/main/stanza/custom-compiler.stanza @@ -9,7 +9,7 @@ defpackage firrtl/custom-compiler : import firrtl/custom-passes public defstruct InstrumentedVerilog <: Compiler : - file: String with: (as-method => true) + with-output: (() -> False) -> False with: (as-method => true) args: List<String> public defmethod passes (c:InstrumentedVerilog) -> List<Pass> : to-list $ [ @@ -36,7 +36,7 @@ public defmethod passes (c:InstrumentedVerilog) -> List<Pass> : RemoveSpecialChars() CheckHighForm() CheckLowForm() - Verilog(file(c)) + Verilog(with-output(c)) ] |
