Added tests for clocks. Added remove scope and special chars passes. Added tests. Made more tests pass

1 files changed, 5 insertions, 3 deletions

diff --git a/src/main/stanza/custom-compiler.stanza b/src/main/stanza/custom-compiler.stanza
index 91732f22..4d63a173 100644
--- a/src/main/stanza/custom-compiler.stanza
+++ b/src/main/stanza/custom-compiler.stanza
@@ -14,7 +14,9 @@ public defstruct InstrumentedVerilog <: Compiler :
 public defmethod passes (c:InstrumentedVerilog) -> List<Pass> :
    to-list $ [
       WhenCoverage(args(c)[0],args(c)[1])
-      CheckHighForm(expand-delin)
+      RemoveSpecialChars()
+      RemoveScopes()
+      CheckHighForm()
       TempElimination()
       ToWorkingIR()
       ;; MakeExplicitReset()
@@ -31,8 +33,8 @@ public defmethod passes (c:InstrumentedVerilog) -> List<Pass> :
       InferWidths()
       SplitExp()
       ToRealIR()
-      SpecialRename(`#,`_)
-      CheckHighForm(expand-delin)
+      RemoveSpecialChars()
+      CheckHighForm()
       CheckLowForm()
       Verilog(file(c))
    ]