diff options
| author | azidar | 2015-06-02 10:41:27 -0700 |
|---|---|---|
| committer | azidar | 2015-06-02 10:41:27 -0700 |
| commit | f8f9de58dbba5e53193246a5fd2145dfe6537e10 (patch) | |
| tree | dedcbc9b1dc7709d6efbc2dce3c5f36303f2a990 /src/main/stanza/compilers.stanza | |
| parent | 8fc826a2770f46d63d8d7b1bccf14d2bf6e6b7cd (diff) | |
Added sequential/combinational memories. Started debugging verilog backend. Added Long support so UInt(LARGENUMBER) works
Diffstat (limited to 'src/main/stanza/compilers.stanza')
| -rw-r--r-- | src/main/stanza/compilers.stanza | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index efa8c992..5a2e2278 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -56,9 +56,11 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> : ExpandIndexedConnects() ExpandWhens() InferWidths() + Pad() SplitExp() ToRealIR() - SpecialRename(`#,`_) + SpecialRename(`#,`__) + SpecialRename(`$,`_) Verilog(file(c)) ] |