diff options
| author | azidar | 2015-12-03 15:12:02 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | c427b31a1ef8361b643d5f7435aeb42472dfe626 (patch) | |
| tree | 6ae504ba1b37b9d0fef281b491cf932ac6826c7b /src/main/stanza/compilers.stanza | |
| parent | ece8ec00868c182e141e8d1ac75bfb60bfaa87ec (diff) | |
WIP. Compiles and almost done with verilog backend. Need to think about emitting ports (and the assignments to them)
Diffstat (limited to 'src/main/stanza/compilers.stanza')
| -rw-r--r-- | src/main/stanza/compilers.stanza | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index 9dda33fe..cfe5bbaf 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -58,6 +58,8 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> : ;CheckTypes() ;R ExpandAccesses() ;W ExpandConnects() ;W + ResolveKinds() ;W + InferTypes() ;R ResolveGenders() ;W ;LowerToGround() ;W ;ExpandIndexedConnects() ;W @@ -65,6 +67,9 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> : ;InferTypes() ;R ;CheckGenders() ;W ExpandWhens() ;W + ResolveKinds() ;W + InferTypes() ;R + ResolveGenders() ;W InferWidths() ;R ;ToRealIR() ;W -> R ;CheckWidths() ;R |