diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /src/main/stanza/compilers.stanza | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'src/main/stanza/compilers.stanza')
| -rw-r--r-- | src/main/stanza/compilers.stanza | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index cfe5bbaf..1598be21 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -77,6 +77,9 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> : ConstProp() ;R SplitExp() ;R LowerTypes() ;R + ResolveKinds() ;W + InferTypes() ;R + ResolveGenders() ;W ;CheckWidths() ;R ;CheckHighForm() ;R ;CheckLowForm() ;R |