diff options
| author | azidar | 2016-01-28 12:12:02 -0800 |
|---|---|---|
| committer | azidar | 2016-01-28 12:12:02 -0800 |
| commit | 9ed79a822f7f406c55af8082da04cb7739e772eb (patch) | |
| tree | 02b10696dd0a03faf54c8eafa046855ccfc26e8f /src/main/stanza/compilers.stanza | |
| parent | b7dcc8ccbb1459a604353a8137081a9b156d276e (diff) | |
| parent | 094c6b8e7b40a3c613547d6127b449d0b1503db3 (diff) | |
Merge branch 'new-reg-prims' of github.com:ucb-bar/firrtl
Diffstat (limited to 'src/main/stanza/compilers.stanza')
| -rw-r--r-- | src/main/stanza/compilers.stanza | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index 3ca4f8da..0d0191bf 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -78,8 +78,6 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> : ;=============== ConstProp() ;=============== - SplitExp() - ;=============== ResolveKinds() InferTypes() CheckTypes() @@ -98,6 +96,8 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> : InferWidths() CheckWidths() ;=============== + VerilogWrap() + SplitExp() VerilogRename() Verilog(with-output(c)) ;=============== @@ -152,8 +152,6 @@ public defmethod passes (c:StandardLoFIRRTL) -> List<Pass> : ;=============== ConstProp() ;=============== - SplitExp() - ;=============== ResolveKinds() InferTypes() CheckTypes() @@ -172,6 +170,8 @@ public defmethod passes (c:StandardLoFIRRTL) -> List<Pass> : InferWidths() CheckWidths() ;=============== + SplitExp() + ;=============== FIRRTL(with-output(c)) ] |