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| author | Adam Izraelevitz | 2015-07-17 16:49:22 -0700 |
|---|---|---|
| committer | Adam Izraelevitz | 2015-07-17 16:49:22 -0700 |
| commit | 70567d4d57ac178660fbef0ef660069b52857562 (patch) | |
| tree | ac0ed0127ddb99a72cbc760f6be97b99c574d018 /src/main/stanza/compilers.stanza | |
| parent | 98bb81d9d99150a80c77ed8f22d44748a02df628 (diff) | |
Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog!
Had to separate initialization check pass
Need to write dead code elimination pass
Added LongWidth to support dshl that are huge
Diffstat (limited to 'src/main/stanza/compilers.stanza')
| -rw-r--r-- | src/main/stanza/compilers.stanza | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index d65e7718..db6781c5 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -65,6 +65,7 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> : RemoveSpecialChars() CheckHighForm() CheckLowForm() + CheckInitialization() Verilog(file(c)) ] |