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authorazidar2015-12-12 14:37:41 -0800
committerazidar2016-01-16 14:28:17 -0800
commit28e4c6a09011cafdd1e3533118f7c3499e0d3dc6 (patch)
tree42e8e2ed50a254f7fea61bc0a56d963258463bb5 /src/main/stanza/compilers.stanza
parentd9f33f58c94382dfbd22e87e2f85600b9807328f (diff)
WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadblock in assigning clocked ports
Diffstat (limited to 'src/main/stanza/compilers.stanza')
-rw-r--r--src/main/stanza/compilers.stanza40
1 files changed, 19 insertions, 21 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index 9e517f10..5cda6325 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -46,40 +46,38 @@ public defmethod backend (c:StandardVerilog) -> List<Pass> :
public defmethod passes (c:StandardVerilog) -> List<Pass> :
to-list $ [
;RemoveSpecialChars() ;R
- ;RemoveScopes() ;R
;CheckHighForm() ;R
;TempElimination() ;R ; Needs to check number of uses
ToWorkingIR() ;R -> W
ResolveKinds() ;W
InferTypes() ;R
ResolveGenders() ;W
+ InferWidths() ;R
+ Resolve()
;CheckGenders() ;W
;CheckKinds() ;W
;CheckTypes() ;R
- ;ExpandAccesses() ;W
- ExpandConnects() ;W
- RemoveAccesses()
- ResolveKinds() ;W
- InferTypes() ;R
- ResolveGenders() ;W
- ;LowerToGround() ;W
- ;ExpandIndexedConnects() ;W
- ;InferTypes() ;R
;CheckGenders() ;W
- ExpandWhens() ;W
- ResolveKinds() ;W
- InferTypes() ;R
- ResolveGenders() ;W
- InferWidths() ;R
+ ExpandConnects()
+ RemoveAccesses()
+ ExpandWhens()
+ ConstProp()
+ SplitExp()
+
+ ResolveKinds()
+ InferTypes()
+ ResolveGenders()
+ InferWidths()
+
+ LowerTypes()
+
+ ResolveKinds()
+ InferTypes()
+ ResolveGenders()
+ InferWidths()
;ToRealIR() ;W -> R
;CheckWidths() ;R
;Pad() ;R
- ConstProp() ;R
- SplitExp() ;R
- LowerTypes() ;R
- ResolveKinds() ;W
- InferTypes() ;R
- ResolveGenders() ;W
;CheckWidths() ;R
;CheckHighForm() ;R
;CheckLowForm() ;R