diff options
| author | azidar | 2016-01-27 14:18:09 -0800 |
|---|---|---|
| committer | azidar | 2016-01-28 09:25:04 -0800 |
| commit | 2428d391d02a9ff413884e073ae3e6ac37f2df2d (patch) | |
| tree | a433fca39129f2642a599643002da66299482aaa /src/main/stanza/compilers.stanza | |
| parent | 067eb9db57f6c9f5f3675d9be11133378531a9b5 (diff) | |
Added addw to working ir as an optimized verilog emission
Diffstat (limited to 'src/main/stanza/compilers.stanza')
| -rw-r--r-- | src/main/stanza/compilers.stanza | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index 3ca4f8da..0d0191bf 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -78,8 +78,6 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> : ;=============== ConstProp() ;=============== - SplitExp() - ;=============== ResolveKinds() InferTypes() CheckTypes() @@ -98,6 +96,8 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> : InferWidths() CheckWidths() ;=============== + VerilogWrap() + SplitExp() VerilogRename() Verilog(with-output(c)) ;=============== @@ -152,8 +152,6 @@ public defmethod passes (c:StandardLoFIRRTL) -> List<Pass> : ;=============== ConstProp() ;=============== - SplitExp() - ;=============== ResolveKinds() InferTypes() CheckTypes() @@ -172,6 +170,8 @@ public defmethod passes (c:StandardLoFIRRTL) -> List<Pass> : InferWidths() CheckWidths() ;=============== + SplitExp() + ;=============== FIRRTL(with-output(c)) ] |