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| author | azidar | 2015-07-10 13:25:21 -0700 |
|---|---|---|
| committer | azidar | 2015-07-14 11:29:55 -0700 |
| commit | 0bfb3618b654a4082cc2780887b3ca32e374f455 (patch) | |
| tree | 230b7cbc96589be229e6f3d87f21300fb8fd84c3 /src/main/stanza/compilers.stanza | |
| parent | 0d63d521de85d1c6b9109e019101d0f575d063f7 (diff) | |
Added clock support
Diffstat (limited to 'src/main/stanza/compilers.stanza')
| -rw-r--r-- | src/main/stanza/compilers.stanza | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index 2f6329dc..c458f1e1 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -15,7 +15,7 @@ public defmethod passes (c:StandardFlo) -> List<Pass> : CheckHighForm(expand-delin) ;; TempElimination() ToWorkingIR() - MakeExplicitReset() + ;; MakeExplicitReset() ResolveKinds() CheckKinds() InferTypes() @@ -45,7 +45,7 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> : CheckHighForm(expand-delin) TempElimination() ToWorkingIR() - MakeExplicitReset() + ;; MakeExplicitReset() ResolveKinds() CheckKinds() InferTypes() |