diff options
| author | azidar | 2015-06-02 17:24:41 -0700 |
|---|---|---|
| committer | azidar | 2015-06-02 17:24:41 -0700 |
| commit | 0a0c2d7c13c5beaa7c5132963112cc9e747ff287 (patch) | |
| tree | ac7c4694e86d939cb693bc25d554284f4326c271 /src/main/stanza/compilers.stanza | |
| parent | eb5ca3c967c929c8331fd17e04dbd9402e41e986 (diff) | |
Added low firrtl check. Corrected bug in prefix matching in high firrtl check
Diffstat (limited to 'src/main/stanza/compilers.stanza')
| -rw-r--r-- | src/main/stanza/compilers.stanza | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index 9f8959ad..f86493a2 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -34,6 +34,7 @@ public defmethod passes (c:StandardFlo) -> List<Pass> : SpecialRename(`#,`_) SpecialRename(`$,`::) CheckHighForm(`::) + CheckLowForm() Flo(file(c)) ] @@ -59,8 +60,10 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> : Pad() SplitExp() ToRealIR() - SpecialRename(`#,`__) - SpecialRename(`$,`_) + SpecialRename(`#,`_) + SpecialRename(`$,`__) + CheckHighForm(`__) + CheckLowForm() Verilog(file(c)) ] |