Added tests for clocks. Added remove scope and special chars passes. Added tests. Made more tests pass

1 files changed, 10 insertions, 9 deletions

diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index c458f1e1..b87c654e 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -12,10 +12,11 @@ public defstruct StandardFlo <: Compiler :
    file: String with: (as-method => true)
 public defmethod passes (c:StandardFlo) -> List<Pass> :
    to-list $ [
-      CheckHighForm(expand-delin)
+      RemoveSpecialChars()
+      RemoveScopes()
+      CheckHighForm()
       ;; TempElimination()
       ToWorkingIR()
-      ;; MakeExplicitReset()
       ResolveKinds()
       CheckKinds()
       InferTypes()
@@ -31,9 +32,8 @@ public defmethod passes (c:StandardFlo) -> List<Pass> :
       Inline()
       SplitExp()
       ToRealIR()
-      SpecialRename(`#,`_)
-      SpecialRename(`$,`::)
-      CheckHighForm(`::)
+      RemoveSpecialChars()
+      CheckHighForm()
       CheckLowForm()
       Flo(file(c))
    ]
@@ -42,7 +42,9 @@ public defstruct StandardVerilog <: Compiler :
    file: String with: (as-method => true)
 public defmethod passes (c:StandardVerilog) -> List<Pass> :
    to-list $ [
-      CheckHighForm(expand-delin)
+      RemoveSpecialChars()
+      RemoveScopes()
+      CheckHighForm()
       TempElimination()
       ToWorkingIR()
       ;; MakeExplicitReset()
@@ -60,9 +62,8 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> :
       Pad()
       SplitExp()
       ToRealIR()
-      SpecialRename(`#,`_)
-      SpecialRename(`$,`__)
-      CheckHighForm(`__)
+      RemoveSpecialChars()
+      CheckHighForm()
       CheckLowForm()
       Verilog(file(c))
    ]