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| author | azidar | 2015-05-19 14:16:06 -0700 |
|---|---|---|
| committer | azidar | 2015-05-19 14:16:06 -0700 |
| commit | 8feaa0a5ae0479b4063771202d7ad0e93d39c247 (patch) | |
| tree | 176dcc3988fd98eef0e1fe3241ded7dcf9d0dfc7 /src/main/stanza/compilers.stanza | |
| parent | 14bb9cda8352388bcd33ba9ca2700805dc51639f (diff) | |
Added support for non-inlined modules in verilog backend
Diffstat (limited to 'src/main/stanza/compilers.stanza')
| -rw-r--r-- | src/main/stanza/compilers.stanza | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index e912d3a0..901f6100 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -52,7 +52,7 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> : ExpandIndexedConnects() ExpandWhens() InferWidths() - Inline() + ;Inline() SplitExp() ToRealIR() Verilog(file(c)) |