diff options
| author | azidar | 2015-10-06 14:28:24 -0700 |
|---|---|---|
| committer | azidar | 2015-10-06 14:28:24 -0700 |
| commit | 2485d20374166b27c06c475a4aef365761a818f7 (patch) | |
| tree | 627b3c180ba41d7619b1acc8be03e2195dd208aa /src/main/stanza/compilers.stanza | |
| parent | 62e922b0e7ea5f90c14a918ab09ce04a28f082d4 (diff) | |
| parent | 0a9dfbe9f58338fc8af11015f6e9227e0cb46ea4 (diff) | |
Merge branch 'master' of github.com:ucb-bar/firrtl
Conflicts:
README.md
Diffstat (limited to 'src/main/stanza/compilers.stanza')
| -rw-r--r-- | src/main/stanza/compilers.stanza | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index 1e978a2e..0ea9a367 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -25,7 +25,7 @@ public defmethod passes (c:StandardFlo) -> List<Pass> : CheckGenders() ExpandAccessors() LowerToGround() - ExpandIndexedConnects() + InlineIndexed() ExpandWhens() InferWidths() Pad() @@ -44,7 +44,7 @@ public defstruct StandardVerilog <: Compiler : public defmethod passes (c:StandardVerilog) -> List<Pass> : to-list $ [ RemoveSpecialChars() ;R - RemoveScopes() ;R + ;RemoveScopes() ;R CheckHighForm() ;R TempElimination() ;R ToWorkingIR() ;R -> W @@ -56,15 +56,17 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> : CheckTypes() ;R ExpandAccessors() ;W LowerToGround() ;W - ExpandIndexedConnects() ;W + ;ExpandIndexedConnects() ;W + InlineIndexed() InferTypes() ;R CheckGenders() ;W ExpandWhens() ;W InferWidths() ;R + ToRealIR() ;W -> R + CheckWidths() ;R Pad() ;R ConstProp() ;R SplitExp() ;R - ToRealIR() ;W -> R CheckWidths() ;R CheckHighForm() ;R CheckLowForm() ;R |