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| author | azidar | 2015-07-10 13:25:21 -0700 |
|---|---|---|
| committer | azidar | 2015-07-10 13:25:21 -0700 |
| commit | 1ed6d4a47c92072b12db4b784f239071e4928049 (patch) | |
| tree | 6849092b4591be05654f931511202a3b1aceb8d1 /src/main/stanza/compilers.stanza | |
| parent | a62fea153cf01e9f7517c6889198d02e5fbbb266 (diff) | |
Added clock support
Diffstat (limited to 'src/main/stanza/compilers.stanza')
| -rw-r--r-- | src/main/stanza/compilers.stanza | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index 2f6329dc..c458f1e1 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -15,7 +15,7 @@ public defmethod passes (c:StandardFlo) -> List<Pass> : CheckHighForm(expand-delin) ;; TempElimination() ToWorkingIR() - MakeExplicitReset() + ;; MakeExplicitReset() ResolveKinds() CheckKinds() InferTypes() @@ -45,7 +45,7 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> : CheckHighForm(expand-delin) TempElimination() ToWorkingIR() - MakeExplicitReset() + ;; MakeExplicitReset() ResolveKinds() CheckKinds() InferTypes() |